Question, i.MX6 measuring SATA signals

[Aemj]

Dear team,

My customer faces the issue that i.MX6D SATA negotiation could fail on the customer’s board.

I recommended checking the SATA signal integrity on the boards.

On the SATA signal checking, the customer needs to use test program for i.MX6.

Do you have any sample software for SATA signal check or SATA compliance test?

Thanks,

Miyamoto

[tonyzheng]

Hi,

Maybe you can try to use some eyediagram software to measure SATA singnal quality. For example, N5411B SATA Compliance Test Software on the link N5411B SATA Compliance Test Software | Keysight (Agilent).

What I can share for imx sata test is as follows:

• Power on the system.Run the SATA test software N5411B on Oscilloscope. Change the output pattern according to software prompt, such as HFTP (High frequency test pattern), MFTP (Mid frequency test pattern), LFTP (Low frequency test pattern), LBP (Lone bit pattern) etc Refer to “53.7.10 BIST Control Register (SATA_BISTCR)” in “i.MX 6Dual/6Quad Application Processor Reference Manual” for more details. Customer could change the patterns by executing the following commands in Linux console

# TXO mode, SSOP

./unit_tests/memtool -32 022000a4=00041700

# TXO mode, HTDP

./unit_tests/memtool -32 022000a4=00041701

# TXO mode, LTDP

./unit_tests/memtool -32 022000a4=00041702

# TXO mode, LFSCP

./unit_tests/memtool -32 022000a4=00041703

# TXO mode, COMP

./unit_tests/memtool -32 022000a4=00041704

# TXO mode, LBP

./unit_tests/memtool -32 022000a4=00041705

# TXO mode, MFTP

./unit_tests/memtool -32 022000a4=00041706

# TXO mode, HFTP

./unit_tests/memtool -32 022000a4=00041707

# TXO mode, LFTP

./unit_tests/memtool -32 022000a4=00041708

• N5411B can output a detailed HTML summary of the testing that includes screen shots taken from the scope.
• Customer should adjust IOMUXC_GPR13 register value for better signal quality according to test result. Detailed information of related Register IOMUXC_GPR13 is provided in the table below.

Field	Description
26–24 SATA_PHY_8	SATA   _PHY Rx - Receiver Equalization control 000   0.5 dB 001   1.0 dB 010   1.5 dB 011   2.0 dB 100   2.5 dB 101   3.0 dB (default) 110   3.5 dB 111   4.0 dB
23–19 SATA_PHY_7	SATA   PHY Rx - Loss of signal detector level. Below the recommended value are shown 10000   SATA1i 10000   SATA1m 11010   SATA1x 10010   SATA2i 10010   (default) SATA2m 11010   SATA2x
18–16 SATA_PHY_6	SATA   PHY Rx - DPLL mode control, sets phase and frequency gain of receiver DPLL For   bits encoding see GPR (IOMUXC_GPR13) below.
15 SATA_SPEED	Indicates   SATA PHY speed mode 0   1.5 GHz 1   3.0 GHz
14 SATA_PHY_5	SATA   PHY - Spread Spectrum Enable. Enables spead spectrum clock production. If the   applied RefClk is already   spread spectrum, this bit must be deasserted. 0   Spread Spectrum disabled 1   Spread spectrum enabled
13–11 SATA_PHY_4	SATA   PHY -Transmit Attenuation control, provides discrete driver attenuation   factors (from full driver level). 000   16/16 001   14/16 010   12/16 011   10/16 100   9/16 (default) 101   8/16 110   Reserved 111   Reserved
10–7 SATA_PHY_3	SATA   PHY Tx -Transmit Boost Control, ratio of drive level of transmission bit to   non transmission bit. 0000   0dB 0001   0.37 dB 0010   0.74 dB 0011   1.11 dB 0100   1.48 dB 0101   1.85 dB 0110   2.22 dB 0111   2.59 dB 1000   2.96 dB 1001   3.33 dB (default) 1010   3.70 dB 1011   4.07 dB 1100   4.44 dB 1101   4.81 dB 1110   5.28 dB 1111   5.75 dB
6–2 SATA_PHY_2	SATA   PHY - Transmit level settings. Fine resolution settings of transmit signal   level, common to all lanes connected to one clock module. 00000   0.937 V 00001   0.947 V 00010   0.957 V 00011   0.966 V 00100   0.976 V 00101   0.986 V 00110   0.996 V 00111   1.005 V 01000   1.015 V 01001   1.025 V 01010   1.035 V 01011   1.045 V 01100   1.054 V 01101   1.064 V 01110   1.074 V 01111   1.084 V 10000   1.094 V 10001   1.104 V (default) 10010   1.113 V 10011   1.123 V 10100   1.133 V 10101   1.143 V 10110   1.152 V 10111   1.162 V 11000   1.172 V 11001   1.182 V 11010   1.191 V 11011   1.201 V 11100   1.211 V 11101   1.221 V 11110   1.230 V 11111   1.240 V
1 SATA_PHY_1	SATA   PHY internal PLL Reference Clock Enable 0   Disable the reference clock to the internal PLL of SATA PHY 1   Enable the reference clock to the internal PLL of SATA PHY
0 SATA_PHY_0	SATA   PHY - Tx Edge rate control enables the SATA PHY to meet the edge rate   requirements for all SATA variants 0   Fast edge rate 1   Medium edge rate

[Aemj]

Hi Tao,

Thanks so much for your support!

The customer tried to use the memtool for measuring SATA signal, but following problem was found.

They monitored SATA TXP signal with their own measure equipment (the capability of the equipment is not so high).

From the measured signal and the linux log, they think as follows.

On the bad boards, SATA communication seems to keep on re-trying OOB(Out-of-band) negotiation after boot-up. SATA communication seems not to reach to speed negotiation.

And on good boards, SATA speed negotiation seems to succeed and the following Linux console log appears.

They are about to measure SATA signal quality by using the facility which can measure SATA signal quality.

To measure SATA signal quality, it is needed that SATA keeps sending a fixed pattern.

And on the bad boards, the memtool command does not work due to the re-trying of OOB signal negotiation. They believe stopping the OOB negotiation retry is needed before using the memtool.

Could you show me the way to stop the OOB negotiation retry?

BestRegards,

Miyamoto

[tonyzheng]

Hi, Miyamoto

Sorry to reply to you so late for Chinese New Year. Where are your Linux console logs? I can't find it.

I don't think the reason that memtool doesn't work is due to the  re-trying of OOB signal negotiation.

Can you check that 53.3.5.14:

Software must ensure that the Port is in idle state and there are no outstanding commands

by checking SATA_P0CI and SATA_P0SACT registers are both cleared, SATA_P 0TFD[STS] register BSY,

DRQ and ERR bits are all cleared.

[Aemj]

Hi Tao,

Sorry for late.

The following is the log from good board.

> ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)

> ata1.00: ATA-8: HGST HTS545050A7E680, GR2OA230, max UDMA/133

> ata1.00: 976773168 sectors, multi 16: LBA48 NCQ (depth 31/32)

> ata1.00: configured for UDMA/133

BR,

Miyamoto

[Aemj]

Hi Tao,

The customer saw SATA_P0CMD= 7Fh by using memtool.

Please look at the attached file.

These files show the two waveforms of TXP of i.MX6 SATA at when i.MX6 is powered-up.

One is measured on bad board and another is measured on OK board.

For the OK board;(linkOK.TIF)

We can see something changed on the waveform at 600mS after the start. And they saw the messages(console log) which indicate speed negotiation succeeded.

> ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)

> ata1.00: ATA-8: HGST HTS545050A7E680, GR2OA230, max UDMA/133

> ata1.00: 976773168 sectors, multi 16: LBA48 NCQ (depth 31/32)

> ata1.00: configured for UDMA/133

For the bad board;(linkdown.TIF)

The waveform keeps same pattern from the start. And they cannot find the similar messages on log as above. After Linux boot up, they saw SATA_P0CMD register is 7Fh(default value).

From the above they believe that OOB signaling cannot complete and OOB signaling keeps on forever. I think that the SATA initialization does not complete.

Is it possible for the OOB signaling not to complete and to keep on?

If so, I think SATA initialization should be done manually by using SDK sample program.

Could you tell me your opinion?

BR,

Miyamoto

[tonyzheng]

Some other advices:

Please check your SATA power line.

According to SATA protocol, When a COMRESET is sent to the device in response to an unsolicited COMINIT, the host shall set the Status register to 7Fh and shall set all other Shadow Command Block Registers to FFh. The unsolicited COMINIT will interrupt normal OOB sequences and let state machine loops back and restart from PHY Reset infinitely.

When the Phy voltage threshold falls below the minimum valuethe, SATA device will issue an unsolicited COMINIT, so the normal OOB sequences is interrupted and Link Layer initialzation failed.

[Aemj]

Hi Tao,

Sorry for my delay.

The customer measured the voltage of the power lines as you said.

But they did not find problems on the voltage.

SATA_VPH:2.52V

SATA_VP:1.22V→1.11V (in allowed range)

From the fact that they cannot measure the signals in the situation of HDD connected.

And memtool cannot be used in the case of SATA link failure.

So, they think they should execute SATA BIST operation from uboot with HDD not connected.

Is it possible?

If so, please let me know the procedure to execute SATA BIST from u-boot.

Thanks,

Miyamoto

[tonyzheng]

Hi, Miyamoto

Please refer to How to generate SATA test pattern on i.mx6?

You can try to use JTAG to set rigister instead of memtool. Also, you can try to use mw command in uboot to set rigister.

[Aemj]

Hi Tao,

The customer tried to set SATA_BISTCR register from uboot as below, but no BIST pattern output was seen.

# TXO mode, LFTP

mw 022000a4 00041708

before setting the BISTCR register, are there any operations needed on other register setting?

Best Regards,

Miyamoto

[tonyzheng]

Please ensure the SATA device is connected and phy link is established.

[norishinozaki]

Hello Tao,

My customer says SATA BIST compliance test is OK except the tests which require to be "Loopback Responder".

In the RM "53.3.5.14 Loopback Responder",  they need to set SATA_TESTR[PSEL].

However i.MX6Q only supports one port (Port0: Default) so they don't need to set anything, correct?

Are there any considerations?

BR,

N.S

[tonyzheng]

Hi, Miyamoto

It seems that the Link Layer initializes failed. I'm not familiar with SATA IC, but in my opinion, there is no way to stop OOB signals and speed negotiation, because this initialization senquence is defined by SATA protocol. Maybe it is your PHY hardware problems. If possible, you can ask hardware AE for help first and then software.

[Aemj]

Dear Tao,

Sorry for hurrying you up but I am still waiting for your comment.

BR,

Miyamoto