First refer to 44.12.53 MMDC PHY CK Control Register in IMX6DQRM(Rev.2).
"DDR clock0 delay fine tuning. This field holds the number of delay units that are added to DDR clock
Next, refer to 17 Clock Delay Calibration in i.MX 6Dual/6Quad DDR Calibration (Rev.0).
To add delay to SDCLK0, SDCLK0_B, configure SDCTRL[SDCLK0_DEL].
To add delay to SDCLK1, SDCLK1_B, configure SDCTRL[SDCLK1_DEL].
Which is right description?
Can we add the delay to CLK0 and CLK1?
Refer to 17 Clock Delay Calibration in i.MX 6Dual/6Quad DDR Calibration (Rev.0).
"Delay unit period is derived from the internal MMDC clock."
How does "Delay unit period" was decided?