About Clock Delay Calibration of DDR3 in i.MX6DQ.

[keitanagashima]

First refer to 44.12.53 MMDC PHY CK Control Register in IMX6DQRM(Rev.2).

"DDR clock0 delay fine tuning. This field holds the number of delay units that are added to DDR clock

(CK0)."

Next, refer to 17 Clock Delay Calibration in i.MX 6Dual/6Quad DDR Calibration (Rev.0).

To add delay to SDCLK0, SDCLK0_B, configure SDCTRL[SDCLK0_DEL].

To add delay to SDCLK1, SDCLK1_B, configure SDCTRL[SDCLK1_DEL].

[Q1]

Which is right description?

Can we add the delay to CLK0 and CLK1?

[Q2]

Refer to 17 Clock Delay Calibration in i.MX 6Dual/6Quad DDR Calibration (Rev.0).

"Delay unit period is derived from the internal MMDC clock."

How does "Delay unit period" was decided?

Best Regards,

Keita

[Yuri]

  Basically, both - section 44.12.53 [MMDC PHY CK Control Register (MMDCx_MPSDCTRL)]

of the Reference Manual and section 17 (Clock Delay Calibration) of the app note AN4467 -
relate to the same registers MMDC1_MPSDCTRL and MMDC2_MPSDCTRL, which are named

as SDCTRL[SDCLK0_DEL] and SDCTRL[SDCLK1_DEL] in the app note.
As mentioned in the app note, “with proper DDR board design, there is no need for the clock
delay, which can be kept to its default 0”.

Regards,

Yuri.

[keitanagashima]

Hi Yuri,

Thank you for your reply.

[Q1]

Let me confirm again.

There was description of "DDR clock0 delay fine tuning. This field holds the number of delay units that are added to DDR clock (CK0)." in 44.12.53 MMDC PHY CK Control Register in IMX6DQRM(Rev.2).

The description looks for only CK0.

Is it possible to add the delay for CK1 by MMDC2_MPSDCTRL register?

[Q2]

I'd like to know the "Delay unit period".

Could you tell me the value of unit?

Best Regards,

Keita

[Yuri]

Keita, hello !

1.
   Yes, it is possible to add the delay for CK1 by MMDC2_MPSDCTRL register.

2.

  The delay elements in the SDCLK path are similar to those in the data strobes

but they are not exactly the same. The delay is on the order of picoseconds,
sorry - not specified exactly.

Regards,

Yuri.

[keitanagashima]

Hi Yuri,

Thank you for your reply.

Q1 is OK. Thank you!

Q2:

Sorry. I couldn't understand well.

For example, if one set the SDclk0_del=10 (Add DDR clock0 delay of 2 delay units.), how much is delay added actually?

Best Regards,

Keia

[Yuri · Accepted solution]

Hi,

> if one set the SDclk0_del=10 (Add DDR clock0 delay of 2 delay units.),

> how much is delay added actually?

Just for estimations (depends on environment - temperature, voltage, etc ) : ~ (4 - 6) ps

Regards,

Yuri.

[keitanagashima]

Hi Yuri,

Thank you for your reply.

Let me clarify my understanding.

Is below understanding right?

- SDclk0_del=01 (Add DDR clock0 delay of 1 delay units.) : 2 - 3 [ps]

- SDclk0_del=10 (Add DDR clock0 delay of 2 delay units.) : 4 - 6 [ps]

- SDclk0_del=11 (Add DDR clock0 delay of 3 delay units.) : 6 - 9 [ps]

And, how did you estimate the delay unit?

Best Regards,

Keita

[Yuri]

Your understanding is correct.

As for delay estimation - you (customer) may provide own measurements
for assurance.

Regards,

Yuri.

[keitanagashima]

Hi Yuri,

Hello.

>As for delay estimation - you (customer) may provide own measurements

>for assurance.

How did you estimate the below delay unit?

(i.e. What did you refer to the data to lead below estimation? Internal data?)

> Just for estimations (depends on environment - temperature, voltage, etc ) : ~ (4 - 6) ps

I couldn't find the how to determine the delay unit...

Best Regards,

Keita

[Yuri]

You may output two waveforms SDclk0 and SDclk1 (assuming the memory controller
is configured and enabled) with delay between both :

SDclk0_del = 0
SDclk1_del = 11

and measure delay between these two channels.

Regards,

Yuri.

[keitanagashima]

Hi Yuri,

OK.

I understood that no specification and one have to measure on actual board.

Best Regards,

Keita