Hello I am using an MCF51QE64 with an I2C module set as a slave with a single master that is an FPGA running an Opencores I2C controller with at the rate of 100KHz.
The issue is that the FPGA master controller issues an arbitration loss error while writing successive bytes to the Coldfire I2C module. The problem turns out to be that the Coldfire after an ACK will hold both the SCL & SDA low for an extended period of time ~2uS which extends the SCL low time. Since this extended time that the Coldfire holds SDA low overlaps when the master is trying to drive SDA high(for the next byte), an arbitration loss error occurs. I know that the SCL is being held low because the clock after the ACK goes from a 4uS on time to a 2uS on-time. Every once in a while the error doesn't happen which tells me it is some kind of timing issue.
The following is the Coldfire register setup
ICSC1 => 0x06 (using internal clock generator)
ICSC2 => 0x00
ICSSC => 0x50 (DCO set to mid level of 32-40MHz)
ICSTRM => this is left at the default setting which is 0x97
IIC1F => 0x0B (we've tried various settings here which seem to change the scope captures but not fix the problem)
IICC1 => 0xC0
If I slow down the Master I2C baud rate to around 50-60KHz everything works without problem. We tried increasing the DCO frequency to the hi-level (48-60MHz) and that increased the probability of success but did not completely fix the problem.
Here is a scope probe. 100 ohm series resistors were added to accentuate the slave pulldown.