Where the encoding for LTSSM states of the PCIe core in the i.MX6 Solo can be found?.

[andresgonzalez]

Hi.

While checking the Debug Register 0, that is part of the Port Logic register of the PCIe Core in the i.MX6 Solo processor we were interesting in knowing the current LTSSM state of the PCIe Core. However the datasheet says:

[5:0]: xmlh_ltssm_state LTSSM current state. See source for encodings

Could somebody tell me where this encoding is located?.

Thanks in advance.

[igorpadykov · Accepted solution]

Hi Andres

`define S_DETECT_QUIET 6'h00

`define S_DETECT_ACT 6'h01

`define S_POLL_ACTIVE 6'h02

`define S_POLL_COMPLIANCE 6'h03

`define S_POLL_CONFIG 6'h04

`define S_PRE_DETECT_QUIET 6'h05

`define S_DETECT_WAIT 6'h06

`define S_CFG_LINKWD_START 6'h07

`define S_CFG_LINKWD_ACEPT 6'h08

`define S_CFG_LANENUM_WAIT 6'h09

`define S_CFG_LANENUM_ACEPT 6'h0A

`define S_CFG_COMPLETE 6'h0B

`define S_CFG_IDLE 6'h0C

`define S_RCVRY_LOCK 6'h0D

`define S_RCVRY_SPEED 6'h0E

`define S_RCVRY_RCVRCFG 6'h0F

`define S_RCVRY_IDLE 6'h10

`define S_RCVRY_EQ0 6'h20

`define S_RCVRY_EQ1 6'h21

`define S_RCVRY_EQ2 6'h22

`define S_RCVRY_EQ3 6'h23

`define S_L0 6'h11

`define S_L0S 6'h12

`define S_L123_SEND_EIDLE 6'h13

`define S_L1_IDLE 6'h14

`define S_L2_IDLE 6'h15

`define S_L2_WAKE 6'h16

`define S_DISABLED_ENTRY 6'h17

`define S_DISABLED_IDLE 6'h18

`define S_DISABLED 6'h19

`define S_LPBK_ENTRY 6'h1A

`define S_LPBK_ACTIVE 6'h1B

`define S_LPBK_EXIT 6'h1C

`define S_LPBK_EXIT_TIMEOUT 6'h1D

`define S_HOT_RESET_ENTRY 6'h1E

`define S_HOT_RESET 6'h1F

Best regards

chip

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