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IMX6 DDR3 DDR21 Parameter clarification

Question asked by Raj Nikumbh on Jul 7, 2014
Latest reply on Jul 7, 2014 by Yuri Muhin

The DQS-CLK output from the controller is specified as +/- 0.25 CLK.  The DRAM’s input by itself allows for a maximum variation of DQS to CLK (tDQSS) of +/-0.25 CLK, which leaves zero margin for any other effects. Can you please look at the parameter called DDR21 given in the datasheet IMX6DQIEC Rev. 2.3, 07/2013?