IMX6 DDR3 DDR21 Parameter clarification

[rajniks]

The DQS-CLK output from the controller is specified as +/- 0.25 CLK.  The DRAM’s input by itself allows for a maximum variation of DQS to CLK (tDQSS) of +/-0.25 CLK, which leaves zero margin for any other effects. Can you please look at the parameter called DDR21 given in the datasheet IMX6DQIEC Rev. 2.3, 07/2013?

[Yuri]

  In general : even through some parameters, measured on i.MX6 pins, do not

provide the margins,  when DDR design follows recommendations (in Hardware

Development Guide for i.MX6), problems should not take place, since (mainly)

only additional delays (because of PCB traces), common for all signals may influence

here.

    As for the DDR3 timings of the i.MX6 : right now we do not have more

data, than provided in the Datasheet. In the future the timings may be

corrected, but I am afraid it will take some time.

  In the same time, we have duty cycle tuning register for clk and dqs, which

can tune the output duty cycle (~1.5%). The tuning function is (by default)

disabled in ddr script. But if we know how the board affect duty cycle, we can

apply the tuning to  compensate it. Please refer to descriptiobn of MMDC Duty

Cycle Control Register (MMDCx_MPDCCR).

Have a great day,
Yuri

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