IMX6S DDR3 x16-Databus and stress test

[thomasgraf]

Hello,

We made a custom design with the IMX6SOLO and only use a single DDR3 chip (MT41J64M16) connected with 16-Bit data bus.

Now we have some trouble to get stable DDR3-Access.

The DCD Data we use when booting from SPI-Flash is like in MX6SNW.txt. We can start u-boot and nearly boot to the linux prompt. But it crashes randomly. When the PCB is worm it is more stable.

Thus I suppose we need to calibrate DDR3 timing parameters.

Unfortunately the stresstest tool never returns any results after starting. The output is in stresstest.txt.

Any hints what might be wrong?

Thomas

Original Attachment has been moved to: stresstest.txt.zip

Original Attachment has been moved to: MX6SNW.txt.zip

[mikhai_i]

Hello Thomas,

I'm hope your choise is iMX6SoloLight?

I should start project  like you(iMX6SLight+DDR3_16bit)...

Could you help me and ansver to my questions:

1.How many layers your PCB have?

2.If you lucky to make it on the 6 layers PCB...could you send me jpegs of the layers PCB ( DDR3 with iMX6SL area).

[andrewsterian]

Hello Thomas,

Having just gone through the pain of this myself (for iMX6SoloLite so not exactly iMX6Solo) here is what I can suggest:

• It is odd in your schematic that you are using CS0 but are driving SDECLK1. Are you sure that's supported?
• I found that the DDR3 Stress Test tool REQUIRES that both chip selects are enabled in the MMDC_MDCTL register, even if you are only using 1 of them. The experience of not doing that is exactly what you observed, it just hangs.
• The documentation for the MMDC_MDASP register is just plain wrong. Please see this forum post: i.Mx6DQSDL DDR3 Script Aid, specifically the reply by Lin Wang on Oct. 17, 2013. The Script Aid tool does NOT generate the right value for this register.

[VladanJovanovic]

Please make sure basic memory controller parameters are configured properly and according to memory device datasheet. Helpful excel sheet for that is located here:

i.Mx6DQSDL DDR3 Script Aid

Typically default values for calibration work OK at room temperature, so I wouldn't look at them as first source of problems (although it might be, if layout/routing is very much different compared to default setup).

But calibration values should be checked and configured as well. I'm not sure of the DDR Stress Tester support for 16-bit wide memories (had some problems in the past for finding calibration values), but if it doesn't work, you can easily write simple JTAG script to perform software-based calibration value search, as described in AN4467 and i.MX 6 reference manual. Example of that for i.MX53 is here : i.MX53 Memory Calibration Script (AN4466)

[thomasgraf]

Unfortunately using that register settings from that Exel sheet doesn't change anything using the stress-test-tool.

And using that as DCD values for uboot doesn't work. My values that are some kind of mix of examples and work "a little" compared to the calculated values.

Interesting might be that writes to MMDC-Registers from uboot immediately stop running any further:

writel((MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET), readl((MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET)));

While reading is no problem and shows the value I've set with DCD-Data.

printf("DDR3: MDPDC: %08X\n", readl((MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET)));

I think I have to see how I can get JTAG-Access to the board :smileysad:

[niklasmolin]

Hi Thomas.

Did you manage to get the test working via JTAG?

I tried on our SabreSD board with a usbWiggler and OcdCommander, but it crashed after a few steps (also tried to initialize all the registers according to the spreadsheet).

When I tried via u-boot, it hangs after it asks what frequency it should run on the DDR and if I try to initialize the registers according to the spreadsheet (in u-boot), it hangs after that (can't even start the stress application).

Regards,

[Yuri]

From GraceH :

In the post of i.MX6 DDR Stress Test Tool V1.0.2

"The image in DDR_Stress_Tester_V1.0.1.zip can't be loaded through sd card. I just attached image DDR_Stress_Tester_V1.0.1_UART1_for_SDboot&JTAG.zip.  The bin files in the packages can be loaded by uboot and elf files are used by JTAG load.  Please note when the image is loaded by u-boot, the DDR is initialized by u-boot."

"

To run ddr stress test from u-boot, CONFIG_SPLASH_SCREEN must be disabled in u-boot.

Because when enter self refresh mode in ddr stress test, DRAM access will be blocked. If splash screen in u-boot is enabled, IPU will continuously access DRAM, so the system will hang up.

"

[thomasgraf]

Unfortunately it's not that easy. We currently suppose that our PCB Layout might be the cause of all DDR3 instability. Next week I hope we have more luck with our next layout revision.

Thanks for your help.