I found this Q&A: How is VPU Latency on i.MX6: Q&A: How is VPU Latency on i.MX6
First, I can't access the referenced discussion: VPU Latency i.MX6. Is there a reason it is blocked?
The answer is not clear enough (at least for me ;-) ).
We need to implement an entire encoding/decoding system like this
Camera => encoder => transmission => decoder => display
What end to end (encoder input to decoder output) latency can we achieve?
We need less then 100ms. Is this possible?
Best regards
Alex
Solved! Go to Solution.
Hi, Alex
The 15ms is average value estimated based one noreorder (only I/P frames exist) for 720p,
In most case, the decoding(or encoding) time for every frame should be less than 15ms.
Basically, the result is not related with core numbers.
ixM6DQ/DL/S are all suppose to be ok.
Eagle
This discussion has been assgned to an engineer internally.
Hi, Alex
The latency discussed in #343081 is about the startup latency, is different with your case.
For your case, I think 100ms is likely possible.
- camera: assume camera capture one frame at 30ms interval
- encoder: one frame delay, ~15ms(720p)
- transmission: ~30 ms ?
- decoder: one frame delay (suppose no reorder in video syntax), ~15ms(720p)
- others: ~10ms
Eagle
Hi Eagle
Thank you for your reply
So the encoding/decoding latency of approx. 15ms is a fact? That would be great news ;-)
I guess this is not related to the number of cores in the device, right?
Any suggestion on a hardware platform to use for a proof of concept?
Best regards
Alex
Hi, Alex
The 15ms is average value estimated based one noreorder (only I/P frames exist) for 720p,
In most case, the decoding(or encoding) time for every frame should be less than 15ms.
Basically, the result is not related with core numbers.
ixM6DQ/DL/S are all suppose to be ok.
Eagle