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Direct MAC-MAC connection to Ethernet switch without a PHY

Question asked by Danielle Loader on Nov 29, 2013
Latest reply on Jan 9, 2016 by Pingli Sui
Branched to a new discussion

Hi iMX community.

 

We have a custom iMX6-based board which includes a Marvell 6350R switch. Our iMX6Q's Ethernet MAC is directly connected to the switch's port 5 MAC via RGMII with 6 nets in each direction: CLK, CTL and D[3:0]. (The switch only has PHYs on ports 0-4)

 

We have been unable to so far to use this interface in either U-Boot or Embedded Linux (Yocto build using fsl-community) despite the switch functioning: we can see it attempting to write packets to the iMX6 at 125MHz but receiving nothing back, not even at reset time. The switch's registers also report that the port is up and running at 125MHz RGMII.

 

I believe we have to use the FIXED_PHY configuration option and provide it with an initialisation structure to allow Linux to use the network interface. We have done this and added the following code to our board.c file in the Linux sources:

 

static struct fixed_phy_status phy_stat __initdata = {
.link   = 1,
.speed  = 1000,
.duplex = 0,
};

 

and in the board init function:

 

fixed_phy_add(PHY_POLL, 0, &phy_stat);

 

This compiles an runs, and in ifconfig we can now see eth0 with status of UP and reporting full duplex.

 

However, no matter what we do there is no activity from the iMX6 to the switch. DHCP requests and pings fail, and ifconfig never reports any activity at all, not even RX packets despite us being able to see them on scope.

 

We have also set (and confirmed by reading back) the following registers in the iMX6:

 

1) Analog ENET PLL Control Register: 0x80082003.

To generate 125MHz ENET clock. PLL lock bit goes high when we do this, so it's working.

 

2) IOMUXC_GPR1 ENET_CLK_SEL: 0x48642005

To use internal TX reference clock for ethernet (instead of a 125MHz input from a PHY)

 

3) Pad Group Control Register: 0x000C0000

IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII to set drive voltage correctly.                

 

And we have set the pin muxing for all these nets which we can again read back correctly. We can also access the switch over MDIO from U-Boot and Linux and toggle its reset state using a GPIO.

 

Is there something else we must do to enable Ethernet communication between these two devices?

 

Thanks

 

Dani

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