To answer your question - I did some checking - I don't think the input to the UART module clock is flexible. Meaning, it comes from PLL3 which is used to create the 480MHz USB clock, and is divided down to 80 MHz for the input to the UART (integer divided by 6). This is per the reference manual of the chip - look for "CCM Clock Tree". PLL3's output is fixed at 20x the input clock to the SOC (usually 24 MHz), so this is 480 MHz.
The baud rate generator for the chip is really flexible, though, so you really shouldn't need to change the input clock to the UART module to achieve the desired baud rate. You should be able to get the exact rate you need using the binary rate multiplier in the UART (BRM). That appears to have the ability to multiply/divide the reference clock using a 16-bit numerator and denominator.
Module Clock 80
Reference Clock 26.66666667
Reference Clock Divider 3
UBMR 1599
UBIR 999
Calculated Baud Rate 1.041666667
Desired Baud Rate 1.041666667
16x desired baud rate 16.66666667
Ratio 1.6
I hope this helps.