AnsweredAssumed Answered

Interrupt latency time (cycles)

Question asked by FabioPacio on Sep 6, 2013
Latest reply on Nov 19, 2015 by Baldur Thorgilsson

Dear all
I'm checking the interrupt latency time of MK60DX256ZVLQ10.

The KQRUG is reporting:

"The NVIC is a standard module on the ARM Cortex M series. This module is closely

integrated with the core and provides a very low latency for entering an interrupt service

routine ISR (12 cycles) and exiting an ISR (12 cycles)."

But, I'm observing a different behaviour. It is possible to check the wave below:

TRACE 1: the edge that generaete the interrupt  (port E pin 0)

TRACE 2: a pin asserted immediately when ISR is started and deasserted at the end of ISR (port A pin 17)

TRACE 3: the TRACE_CLKOUT pin with system clock/2.




This is my simple ISR:



PORTE_ISFR |= 0x01;

GPIOA_PDOR |= 0x00020000;

GPIOA_PDOR &= ~0x00020000;




Can someone tell me why the latency is too big than 12 cycles?


thank you all..