32bit read access on 16bit eLBC (GPCM) - MPC8313E

[wonderwizard]

Hi,

I have never used a freescale device before. If I perform a 32bit read / write on the 16bit eLBC does the (GPCM) eLBC controller split the single 32bit transaction into two 16bit transactions or is just the LSW used resulting in only 1 eLBC transcation being performed? I have not been able to find any crystal clear documentation on this, I think the MPC8313ERM section 10.5.3 is unclear.

I am creating a FPGA interface between the 16bit eLBC GPCM and a 32bit FPGA data bus.

Thanks in advance.

Chris

Message was edited by: Chris W - added GPCM info

[alexander_yakov]

In MPC8313 device - any 32-bit access to 16-bit GPCM target will be automatically split by local bus controller to two consecutive accesses, and these accesses will be performed in back-to-back manner. This is for both read and write.

Message was edited by: Alexander Yakovlev

[wonderwizard]

It is still not clear to me how 32bit accesses are 'split' on the eLBC on the MPC8313E.

[alexander_yakov]

It will be split automatically by local bus controller and transparently for user software. From your FPGA side, it will look like two 16-bit accesses with incremented addresses (as if you run two discrete 16-bit transactions in your code).

When user software issues 32-bit access, this access will be initiated by e300 core as one 32-bit bus transaction, arbitrated on internal bus and reach local bus controller as one 32-bit bus transaction. The local bus controller, acting as target on internal bus, will accept this transaction and automatically split it to two consecutive 16-bit accesses, if the target memory device is configured as 16-bit in ORx/BRx register pair.

Note, this is for 32-bit accesses, aligned to 32-bit boundary. For non-aligned (misaligned) accesses the behavior of e300 core will be more complex. Misaligned access will be broken by e300 core to discrete accesses, and each access will be arbitrated individually on the internal bus.

[wonderwizard]

Thanks Alexander, this is now much clearer for me.

I do have one more question about the addressing of LSW MSW accesses.

I have the following scenario, 8313 accessing 32bit FPGA registers via a 16bit eLBC. I had planned to have my FPGA peripherals on 4K boundaries, all with 32bit registers, ie peripheral A 0x1000, peripheral B 0x2000 etc. Peripheral A at Address 0x1000 has two 32bit registers 0x1000 and 0x1004.

Am I correct in saying that if I do this then a 32bit access to 0x1000 will result in two 16bit beat cycles.

1st beat cycle LSW

addr 0x1000

2nd beat cycle MSW

addr 0x1001  ie LSbit  = '1'

so I need to decode the address LSbit to determine whether the upper or lower word is accessed?

Thanks

Chris

Message was edited by: Chris W

[alexander_yakov · Accepted solution]

For MPC8313 processor, each address value addresses one byte of memory. So, when your memory device width is 16-bits (2 bytes), least significant bus address is not used for connection.

MPC8313 Reference Manual, Table 10-2:

LA[0:25]

Nonmultiplexed address bus. All bits driven on LA[0:25] are defined for 8-bit port sizes. For 16-bit port sizes LA[25] is a don’t care.

For 16-bit memory device address will be incremented by +2:

1st beat - to 0x1000

2nd beat - to 0x1002

From your FPGA device side, as long as least significant address is not visible, it will be seen as:

0x800

0x801

Where each address value addresses one 16-bit FPGA entry.

[marius_grigoras]

Hi Alexander,

Can you please be more verbosely ? When you said "will be split" it means that the user must split these accesses (e.g. in software if I want to read 32bits I need to use 2 unsigned short instructions?) or the controller will make this transparently for us? For write I'm pretty sure that the user must use 2 accesses, but for read my guess is that the controller will split the 32bits accesses in 2 consecutive 16bits accesses.

Taking a look in our NOR flash code, indeed for any 16bits devices we're using specific 16bits instructions for both read and write, but for read I think this was made just for code granularity.

Regards,

Marius

[alexander_yakov]

"Will be split" means it will be split automatically by local bus controller, this will be done transparently for user for both read and write transactions. You do not have to use two 16-bit transactions for write.

Updated my reply already.

[marius_grigoras]

Hi Chris,

All devices mapped through GPCM interfaces can be read directly because are memory-mapped, so for read operations it will be perform a single 32bit transaction. In the case of write, it must be 2 16bit transactions. Please note that my answer is related to NOR flash functionality but it should be applicable as well for FPGA (because NOR is also memory-mapped via GPCM).

Regards,

Marius

[wonderwizard]

Marius,

Thanks, can I please ask you to clarify your statement.

Marius Viorel Grigoras wrote:

So for read operations it will be perform a single 32bit transaction. In the case of write, it must be 2 16bit transactions.

Read:

Software reads a 32bit register which happens to be memory mapped over the 16bit eLBC IF. The eLBC performs two eLBC 16bit read cycles automatically and the complete 32bit data register is then available after the second bus read cycle?

Write:

No support for writing a 32bit register directly? TheMPC8313E software needs to write the first 16bits then second 16bits, ie it needs to know there is a 16bit eLBC and address the top half and bottom half words?