I'm designing hardware that interfaces a K60P100M100 MCU with an Ethernet physical interface. I am looking for a reference design that includes the connection details of the PHY chip (such as a KSZ8041NL) to the K60, including the optimal configuration for clocks etc.... Probably an RMII rather than MII interface.
The TWR-SER board has lots of superfluous links and configuration options which I'm finding confusing as a reference design. For example I don't believe I would need the NB2304 clock distribution chip if both the MCU and PHY are running from a single 50MHz clock.
Some references have also indicated that the RMII mode is preferred as there is overlap on some devices with the JTAG interface.
Can anyone point me to a schematic for this already done on the same PCB? Help appreciated.