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i2c: Is This a Bug?

Question asked by swarga on Oct 25, 2012
Latest reply on Jul 12, 2017 by Nikita Vostokov

I have a design based on the MPC8349EA processor. While perusing the driver source from my Linux 2.6.35.2 kernel (drivers/i2c/busses/i2c-mpc.c) I came across the following function:

 

/* Sometimes 9th clock pulse isn't generated, and slave doesn't release

* the bus, because it wants to send ACK.

* Following sequence of enabling/disabling and sending start/stop generates

* the pulse, so it's all OK.

*/

static void mpc_i2c_fixup(struct mpc_i2c *i2c)

{

        writeccr(i2c, 0);

        udelay(30);

        writeccr(i2c, CCR_MEN);

        udelay(30);

        writeccr(i2c, CCR_MSTA | CCR_MTX);

        udelay(30);

        writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);

        udelay(30);

        writeccr(i2c, CCR_MEN);

        udelay(30);

}

 

Indeed, while working with the i2c, I have occasionally experienced an i2c bus hang while waiting for the ACK from the slave which this little kludge recovers from. My question is why is this needed? Is this a bug in the i2c peripheral? I see no mention of this in the errata sheet.

 

Thanks for any insight.

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