Rx Error When running two UCCs in Parallel

[subashrajaram]

Hi Folks

We are using MPC8309 as well as MPC8321 in our project. Here I have two questions

1) When I use two UCCs in the SDLC mode simultaneously then I see One of the UCC has the Rx Packet drops and in other one there is no such a loss.

When I explore on this, there is Rx Interrupts at all. So I Dumped the Buffer descriptors. The length field is not updated. The expected value of the Buffer descriptor in case of no reception is 0x9000 but the value obtained is 0x9c00. So I am considering that F and L bit are set by the RISC but the legth is not updated. What may be the Reason? If I run the Single port alone, then there is no such a Rx loss.

2) The Control Signals CTS, RTS and CD should be shorted if we use the UCC in Loop-back mode or else those signals should be driven according to the third party device. But the requirement is to run the ports in HDLC mode without shorting the CTS/RTS/CD pins. \

So we tried by configuring those pins as GPIOs with the following values.
For Example, I am using UCC2 . Following are the pins and their corresponding CPPAR and CPDIR values.
PINS: PA26, PA28 and PA30
CPPAR_REGS: 00, 00 and 00
CPDIR_REGS: 11, 11 and 11

But the loopback fails. Are we doing anything wrong?

Thanks in advance.

alexander.yakovlev‌

[subashrajaram]

Hi Alexander,

Thanks for your quick response.

Reply for answer 1: 

Previously I was using the Clock speed of 153.6K and now I reduced the speed to 19.2K. But still the problem exists. I tried out few cases. Out of those cases the Rx Drop doesn't happen only when I use read/write buffer size as 32bytes minimum. If I reduce the buffer size less than 32bytes, again I see the Rx Drop. Is there any possibility that Buffer size play a role in the error?

In addition to this, If an UCC is initialized  when other UCC is running (doing Tx and Rx), at that time also there is Rx drop (only till the UCC initialization completes). There is no packet drop after that UCC initialization. Why Rx drop happens during the initialization?

Reply for Answer 2: 

Yes. Tried the configurations whatever you mentioned in the reply. CDP and CTSP is set to '0' . The CTS and CD pins are configured as GPO pins. But still the loop back doesn't succeed. Attached the register dumps for you kind reference. Please let me know if i configured anything wrong.

UCC2 Fast registers:
gumr : val=0x01800030
upsmr : val=0x30000000
utodr : val=0x0000
udsr : val=0x7e7e
ucce : val=0x00000000
uccm : val=0x009f0000
uccs : val=0x00
urfb : val=0x00000200
urfs : val=0x0100
urfet : val=0x0080
urfset: val=0x00c0
utfb : val=0x00000100
utfs : val=0x0100
utfet : val=0x0080
utftt : val=0x0040
utpt : val=0x0100
urtry : val=0x00000000
guemr : val=0x13

Dumping UCC 2 Parameter RAM
ucc_hdlc : rbase = 0x7017000
ucc_hdlc : rbptr = 0x0
ucc_hdlc : mrblr = 0x800
ucc_hdlc : rbdlen = 0x0
ucc_hdlc : rbdstat = 0x0
ucc_hdlc : rstate = 0x30000000
ucc_hdlc : rdptr = 0x0
ucc_hdlc : riptr = 0x320
ucc_hdlc : tbase = 0x36c3000
ucc_hdlc : tbptr = 0x36c3018
ucc_hdlc : tbdlen = 0x20
ucc_hdlc : tbdstat = 0x9c00
ucc_hdlc : tstate = 0x3004001f
ucc_hdlc : tdptr = 0x6211800
ucc_hdlc : tiptr = 0x380
ucc_hdlc : rcrc = 0x0
ucc_hdlc : tcrc = 0x0
ucc_hdlc : c_mask = 0xf0b8
ucc_hdlc : c_pers = 0xffff
ucc_hdlc : disfc = 0x0
ucc_hdlc : crcec = 0x0

Dump tx BDs
0xc36c3000: 1c000020 06210000 1c000020 06210800
0xc36c3010: 1c000020 06211000 9c000020 06211800
0xc36c3020: 14000000 06212000 14000000 06212800
0xc36c3030: 14000000 06213000 14000000 06213800
0xc36c3040: 14000000 06214000 14000000 06214800
0xc36c3050: 14000000 06215000 14000000 06215800
0xc36c3060: 14000000 06216000 14000000 06216800
0xc36c3070: 14000000 06217000 34000000 06217800

Dump rx BDs
0xc7017000: 90000000 06200000 90000000 06200800
0xc7017010: 90000000 06201000 90000000 06201800
0xc7017020: 90000000 06202000 90000000 06202800
0xc7017030: 90000000 06203000 90000000 06203800
0xc7017040: 90000000 06204000 90000000 06204800
0xc7017050: 90000000 06205000 90000000 06205800
0xc7017060: 90000000 06206000 90000000 06206800
0xc7017070: 90000000 06207000 90000000 06207800
0xc7017080: 90000000 06208000 90000000 06208800
**************End of the Log*********

[alexander_yakov]

Fro question #1:

The first what comes to mind is QE performance issue. If each channel works perfect, abut two channels simultaneously do not work and produce random behavior, than it might be internal QE RISC processor performance is not enough to sustain both channels simultaneously.

Please try reducing channel speed and check if two channels can run simultaneously, but at two times reduced speed.

For question #2:

RTS is output signal, you do not need to take care about this signal. CTS and CD are inputs and should be configured properly, if not used. Please look MPC8321 Reference Manual, Table 3-11. In this table you can see column "Default input", showing "GND" for both SER2_CD and SER2_CTS. This means - if this particular pin is configured to any other function, for example - to GPO,  internal UCC input SER2_CD will be connected internally to GND.

In addition to the above, you should also configure CDP and CTSP bits in UCC mode register to "0" to envelope data. This settings allows leaving CTS and CD permanently asserted.

Have a great day,
Alexander
TIC

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[subashrajaram]

Hi Alexander,

Thanks for your quick response.

Reply for answer 1:

Previously I was using the Clock speed of 153.6K and now I reduced the

speed to 19.2K. But still the problem exists. I tried out few cases. Out of

those cases the Rx Drop doesn't happen only when I use read/write buffer

size as 32bytes minimum. If I reduce the buffer size less than 32bytes,

again I see the Rx Drop. Is there any possibility that Buffer size play a

role in the error?

In addition to this, If an UCC is initialized when other UCC is running

(doing Tx and Rx), at that time also there is Rx drop (only till the UCC

initialization completes). There is no packet drop after that UCC

initialization. Why Rx drop happens during the initialization?

Reply for Answer 2:

Yes. Tried the configurations whatever you mentioned in the reply. CDP and

CTSP is set to '0' . The CTS and CD pins are configured as GPO pins. But

still the loop back doesn't succeed. Attached the register dumps for you

kind reference. Please let me know if i configured anything wrong.

With Warm Regards,

Subash Rajaram

VVDN Technologies Pvt Ltd <http://www.vvdntech.com/>

Mobile: +91 8903001376 | Skype: subashjayaraj25

On Mon, Jun 26, 2017 at 12:04 PM, alexander.yakovlev <