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DMA and UART questions

Question asked by pmt on Aug 7, 2012
Latest reply on Sep 20, 2018 by Mark Butcher


I'm writing a DMA driven UART driver, concentrating on the TX side first.  Please help me understand the "UART DMA Service Request" and "Basic Transfer" interaction.  First, what is the condition under which the service request is asserted by the UART?  Is this the TDRE condition?  Is this service request to the DMA level or edge sensitive?


I presume that in the case of the UART TX, the DMA minor loop must be set to 1 (I'm assuming only a one byte FIFO of UART2 to 5), and that the "Basic Transfer" or "Minor Loop" will not throttle based on the state of the DMA request?  If so this requires a minor loop of one, and a major loop count that holds the number of bytes to transfer.


If this is the case, is there a coherent way to append to the major loop count (for a subsequent write to the UART) even with a DMA in progress?  For instance, by stopping DMA first?  I would like to try to avoid using interrupts to chain the next DMA transfer.