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Problem configuring K20 to use an external crystal...

Question asked by Alex Thompson on Jan 16, 2012
Latest reply on Oct 26, 2012 by Peng Liang

We've had trouble nailing down our system clock speed when the board heats up (turns out there's an errata on that) but, fortunately, we've got a 32k crystal hooked up to [E]XTAL32 for a RTC we didn't end up using. So, as far as I can tell, we can route the RTC through to the FLL clock to get a 96Mhz system clock.

 

My original code didn't work, and neither did the code I pulled from processorexpert so I'm left assuming I've stuffed up somewhere.

 

Here's what I've pulled from PE:

Spoiler

SIM_SCGC6 |= (uint32_t)0x20000000UL; 

if ((RTC_CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */
  /* RTC_CR: SC2P=0,SC4P=1,SC8P=1,SC16P=0 */
  RTC_CR &= (uint32_t)~0x3C00UL; 
  RTC_CR|=(0b0110<<10);
  /* RTC_CR: OSCE=1 */
  RTC_CR |= (uint32_t)0x0100UL; 
  /* RTC_CR: CLKO=1 */
  RTC_CR |= (uint32_t)0x0200UL; 
}


/* Disable the WDOG module */
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
WDOG_UNLOCK = (uint16_t)0xC520U; /* Key 1 */
/* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
WDOG_UNLOCK = (uint16_t)0xD928U; /* Key 2 */
/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKsrc=1,WDOGEN=0 */
WDOG_STCTRLH = (uint16_t)0x01D2U; 

/* System clock initialization */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = (uint32_t)0x01330000UL; /* Update system prescalers */
/* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
SIM_CLKDIV2 = (uint32_t)((SIM_CLKDIV2 & (uint32_t)~0x0DUL) | (uint32_t)0x02UL); /* Update USB clock prescalers */
/* SIM_SOPT2: PLLFLLSEL=0 */
SIM_SOPT2 &= (uint32_t)~0x00010000UL; /* Select FLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=1 */
SIM_SOPT1 |= (uint32_t)0x00080000UL; /* RTC oscillator drives 32 kHz clock for various peripherals */
/* Switch to FEE Mode */
/* OSC_CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC_CR = (uint8_t)0x00U; 
/* SIM_SOPT2: MCGCLKSEL=1 */
SIM_SOPT2 |= (uint32_t)0x01UL;
SIM_SOPT2=1;

/* MCG_C2: ??=0,??=0,RANGE=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
MCG_C2 = (uint8_t)0x00U; 
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG_C1 = (uint8_t)0x00U; 
/* MCG_C4: DMX32=1,DRST_DRS=3 */
MCG_C4 |= (uint8_t)0xE0U; 
/* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
MCG_C5 = (uint8_t)0x00U; 
/* MCG_C6: LOLIE=0,PLLS=0,CME=0,VDIV=0 */
MCG_C6 = (uint8_t)0x00U;

 

while((MCG_S & MCG_S_IREFST_MASK) != 0x00U); /* Check that the source of the FLL reference clock is the external reference clock. */
while((MCG_S & 0x0CU) != 0x00U); /* Wait until output of the FLL is selected */

 

The code hangs on the second-last line there, waiting for the status bit to set to show the external reference has been selected. Debugger shows the MCG_C1->IREFS=0.

 

Cheers.

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