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About Ahmad_bozorgi
About Ahmad_bozorgi
Ahmad_bozorgi
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Activity Feed
Got a Kudo for
download scst library?
.
07-25-2021
10:59 PM
Posted
operation?Re: why instruction accesses add one wait state at the core?
on
S32K
.
10-18-2020
05:05 AM
Kudoed
Re: why instruction accesses add one wait state at the core?
for danielmartynek.
10-18-2020
05:04 AM
Posted
how to use MB for transmit in FlexCAN when RXFIFO is active?
on
S32K
.
10-06-2020
11:27 PM
Posted
Re: why instruction accesses add one wait state at the core?
on
S32K
.
10-06-2020
10:06 PM
Posted
why instruction accesses add one wait state at the core?
on
S32K
.
10-05-2020
10:19 PM
Posted
cache vs FMC controller difference?
on
S32K
.
10-05-2020
10:09 PM
Kudoed
Re: How can I define variable in S32K146 RAM_U
for dianabatrlova.
10-03-2020
04:43 AM
Kudoed
Re: write in D-Flash (or P-flash) with IAP? (in application programming)
for lukaszadrapa.
10-03-2020
04:40 AM
Kudoed
Re: FlexNVM Memory data retention ?
for danielmartynek.
10-03-2020
04:37 AM
Posted
FlexNVM Memory data retention ?
on
S32K
.
09-30-2020
10:46 PM
Kudoed
Re: How to implement core self-check
for lukaszadrapa.
09-30-2020
05:37 AM
Posted
write in D-Flash (or P-flash) with IAP? (in application programming)
on
S32K
.
09-30-2020
05:31 AM
Posted
Re: How to implement core self-check
on
S32K
.
09-29-2020
05:15 AM
Kudoed
Re: Why is SRAM split, and what does it mean?
for rastislav_pavlanin.
09-26-2020
09:09 PM
Kudoed
Re: Low power and Doze Mode question in S32K
for victorjimenez.
09-25-2020
11:30 PM
Kudoed
Re: why SRAM segmented to two banks?
for davidtosenovjan.
09-25-2020
11:24 PM
Posted
Re: How can I define variable in S32K146 RAM_U
on
S32K
.
09-23-2020
05:06 AM
Kudoed
Re: How can I define variable in S32K146 RAM_U
for dianabatrlova.
09-23-2020
05:04 AM
Posted
Re: How can I define variable in S32K146 RAM_U
on
S32K
.
09-23-2020
12:31 AM
Latest posts by Ahmad_bozorgi
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Views
Posted
operation?Re: why instruction accesses add one wait state at the core?
S32K
2711
10-18-2020
05:05 AM
how to use MB for transmit in FlexCAN when RXFIFO is active?
S32K
2706
10-06-2020
11:27 PM
Re: why instruction accesses add one wait state at the core?
S32K
2748
10-06-2020
10:06 PM
why instruction accesses add one wait state at the core?
S32K
2762
10-05-2020
10:19 PM
cache vs FMC controller difference?
S32K
1756
10-05-2020
10:09 PM
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Kudos received
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