why instruction accesses add one wait state at the core?

[Ahmad_bozorgi]

Hi.

I have 2 question about memory,

1.why instruction accesses add one wait state at the core?

2. why backdoor access to SRAM (L or U) needs "Minimum two cycles for  read and one cycle for write"? is that correct "if we use DMA as a master for access data in SRAM, speed will be decreased"?

Thanks.

[danielmartynek]

Hi Ahmad,

1.

Could you elaborate?

Instructions can be fetched from the Cache, SRAM or from the Flash module via the Crossbar switch.

2.

The DMA accesses SRAM through the Crossbar switch, it can't access SRAM directly like the core.

Regards,

Daniel

[Ahmad_bozorgi]

Thanks for your kind reply.

Thanks for kind reply. why read wants more cycle rather than read?

[Ahmad_bozorgi]

Thanks for reply. 

1. in "AN4745" it mentioned:

Core has access to SRAM_U from System bus which its speed is like I/D Bus. so Where does this delay come from?

2. it RM says that crossbar connect masters to slaves simultaneously, so there is should not be delay! (in my opinion). you say because of the crossbar, DMA access speed to SRAM, will be less than Core? (i.e. Core clock = 80MHz, sys_clk = 80MHz, DMA access clock will be 80MHz or less?)

[danielmartynek]

Hi Ahmad,

To both the questions, this is not about the clock but the architecture.

1.

You may refer to this thread:

https://community.nxp.com/t5/Kinetis-Microcontrollers/Internal-SRAM-wait-states/m-p/386848

2.

I see you meant something different.

But anyway, there is arbitration in the crossbar switch and in the SRAM controller which can delay the access.

Regards,

Daniel