iMXRT1010 enabling GPIO2 causes hard fault

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iMXRT1010 enabling GPIO2 causes hard fault

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youngSheldon
Contributor III

Hi community,

I have an application based on EVK of iMXRT1010 and I need many IOs. As a consequence I decided to use PIN62, which is unused on the board, being connected only to TP33. It belongs to GPIO2 and I use the CConfigTools->Pins for it. I succesfully configured several pins from GPIO1, but as soon as I enable the PIN62, I run into a hard faulu as seen in pics below. Any ideas are much appreciated.

It crashes at the last line (generated code in pin.mux) but works fine if GPIO2 related code is removed:

IOMUXC_SetPinMux(IOMUXC_GPIO_SD_12_GPIO2_IO12, 0U);

IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &

(~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK)))

| IOMUXC_GPR_GPR26_GPIO_SEL(0x00U)

);

IOMUXC_SetPinConfig(IOMUXC_GPIO_11_GPIOMUX_IO11, 0x10A0U);

youngSheldon_0-1755197796507.png

youngSheldon_1-1755197997690.png

 

 

let it flow
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Pablo_Ramos
NXP Employee
NXP Employee

Hi @youngSheldon,

FlexSPI_DQS needs to be floating for QSPI Flash RW @133MHz (default), in this case PIN62 is DQS Reserved.

If you link the application to RAM, you should be able to configure PIN62.

Pablo_Ramos_0-1755627040086.png

Best Regards,
Pablo

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Pablo_Ramos
NXP Employee
NXP Employee

Hi @youngSheldon,

FlexSPI_DQS needs to be floating for QSPI Flash RW @133MHz (default), in this case PIN62 is DQS Reserved.

If you link the application to RAM, you should be able to configure PIN62.

Pablo_Ramos_0-1755627040086.png

Best Regards,
Pablo

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youngSheldon
Contributor III

Thanks for the reply Pablo.

I was expecting the PIN Mux Settings to take ofer and DQS to be ignored and left floating inside the chip. I was so wrong...

let it flow
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