iMIMXRT595 I3C DDR Mode not working at 12.5Mhz

[sai_sudheer]

<Priority>

We are experiencing data corruption in I3C HDR-DDR mode at 12.5MHz on the MIMXRT595-EVK board. The issue is specific to higher frequencies and does not occur at lower speeds.

Problem Details:

• Hardware: MIMXRT595-EVK
• Mode: I3C HDR-DDR
• Frequency: 12.5MHz (EXAMPLE_I3C_PP_BAUDRATE = 12500000U)
• Expected Data: Sequential pattern (0, 1, 2, 3)
• same as SDK example i3c_polling_b2b_transfer/mastter, slave 
• Received Data: Corrupted pattern [1, 0, 2, 1] (tried for reduced samples as when samples increases communication handoff is not happening from slave to master)
• Working Frequencies: 4MHz, 6.25MHz (no data corruption)

along with this, We need clarification on I3C clock frequency generation capabilities and proper configuration methods for the RT595.

Observed Behavior:

• Only specific frequencies are achievable: <4MHz, 6.25MHz, 12.5MHz
• Intermediate frequencies (5MHz, 7MHz, 8MHz, 10MHz) all result in 6.25MHz output
• Clock source appears fixed regardless of EXAMPLE_I3C_PP_BAUDRATE setting

What are ALL supported I3C frequencies on RT595?

Can we configure intermediate frequencies (e.g., 8MHz, 10MHz) by changing the source clock, and if so, how?

[Harry_Zhang]

Hi @sai_sudheer 

About the  How to configure the baud rate.

I think you can refer to the void void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz) function.

This function is located in the fsl_i3c.c.

BR

Harry