i.MXRT1170: XBAR problems with chained DMAs

[michael_fischer]

Hello forum,
Hello @Kan_Li 

last time I got the hint from you that the “XBARA1_InputDmaDone0” is only an pulse and not a high signal. Reference is made to my old post here: https://community.nxp.com/t5/i-MX-RT/i-MXRT1170-How-to-route-kXBARA1-InputDmaDone0-through-XBAR1/m-p... 

Reference is made to the i.MXRT1170-EVKB board.

The “DmaDone” with the XBAR is working if the DMA is started by the write to the SERQ register. In this case the setup of the DMA, here DMA1 looks like:

static void DMAInitChannel1 (void)
{
   edma_transfer_config_t transferConfig;

   DMAMUX_EnableAlwaysOn(DMAMUX0, 1, true);
   DMAMUX_EnableChannel(DMAMUX0, 1);

   EDMA_CreateHandle(&dmaHandle1, DMA0, 1);
   EDMA_ResetChannel(dmaHandle1.base, dmaHandle1.channel);

   memset(&transferConfig, 0x00, sizeof(transferConfig));
   EDMA_PrepareTransfer(&transferConfig,
                        (void*)&srcBuffer1[0],
                        32,
                        (void*)&destBuffer[8],
                        32,
                        32,
                        32,
                        kEDMA_MemoryToMemory);
   EDMA_SubmitTransfer(&dmaHandle1, &transferConfig);
   EDMA_SetMajorOffsetConfig(DMA0, 1, -32, -32);
   EDMA_SetCallback(&dmaHandle1, EDMA_Callback, NULL);
   XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputDmaDone1,  kXBARA1_OutputIomuxXbarInout38);

} /* DMAInitChannel1 */

Here the DMA1 can be started several times with the following command:

EDMA_StartTransfer(&dmaHandle1);

Every time the DMA1 is working, and the GPIO pulse is available on the oscilloscope.

========================================================================

But if I used a chained DMA, that mean I will linked DMA0 with DMA1 and start DMA0. The pulse is not available anymore on the oscilloscope. The new code looks like:

static void DMAInitChannel0 (void)
{
   edma_transfer_config_t transferConfig;

   DMAMUX_EnableAlwaysOn(DMAMUX0, 0, true);
   DMAMUX_EnableChannel(DMAMUX0, 0);

   EDMA_CreateHandle(&dmaHandle0, DMA0, 0);
   EDMA_ResetChannel(dmaHandle0.base, dmaHandle0.channel);

   memset(&transferConfig, 0x00, sizeof(transferConfig));
   EDMA_PrepareTransfer(&transferConfig,
                        (void*)&srcBuffer0[0],
                        32,
                        (void*)&destBuffer[0],
                        32,
                        32,
                        32,
                        kEDMA_MemoryToMemory);
   EDMA_SubmitTransfer(&dmaHandle0, &transferConfig);
   EDMA_SetMajorOffsetConfig(DMA0, 0, -32, -32);

} /* DMAInitChannel0 */

static void DMAInitChannel1 (void)
{
   edma_transfer_config_t transferConfig;

//   DMAMUX_EnableAlwaysOn(DMAMUX0, 1, true);
//   DMAMUX_EnableChannel(DMAMUX0, 1);

   EDMA_CreateHandle(&dmaHandle1, DMA0, 1);
   EDMA_ResetChannel(dmaHandle1.base, dmaHandle1.channel);

   memset(&transferConfig, 0x00, sizeof(transferConfig));
   EDMA_PrepareTransfer(&transferConfig,
                        (void*)&srcBuffer1[0],
                        32,
                        (void*)&destBuffer[8],
                        32,
                        32,
                        32,
                        kEDMA_MemoryToMemory);
   EDMA_SubmitTransfer(&dmaHandle1, &transferConfig);
   EDMA_SetMajorOffsetConfig(DMA0, 1, -32, -32);
   EDMA_SetCallback(&dmaHandle1, EDMA_Callback, NULL);
   XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputDmaDone1,  kXBARA1_OutputIomuxXbarInout38);

   EDMA_SetChannelLink(DMA0, 0, kEDMA_MajorLink, 1);

} /* DMAInitChannel1 */

And the chained  DMA can be started with:

EDMA_StartTransfer(&dmaHandle0);

Here the data will be transferred by DMA0 and DMA1, but the “DmaDone1” will not produce the GPIO pulse anymore.

It looks that the XBAR functionality is only working here if the DMA was started by the SERQ regsiter and not internaly by the link functionality.

Do you have any hints for me?

Best regards,
Michael

[michael_fischer]

Some more information.

It looks that the XBAR functionality is only working here if:

• the DMAMUX0.CHCFG[x].ENBL bit is set for the corresponding DMA channel and,
• the DMAMUX0.CHCFG[x].A_ON bit is set for the corresponding DMA channel and,
• the DMA was started by the SERQ register.

It looks that it is not working if it is started:

• internally by the link functionality, or
• by setting the TCDx_CSR.START bit of the corresponding DMA channel

[Kan_Li]

Hi @michael_fischer ，

I believe that is due to DMA channel 1 is a linked channel, as I can always catch the done signal out of DMA channel 0, even it was linked to channel 1. I will check with the expert if it is an expected result.

Have a great day,
Kan

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[michael_fischer]

Hello @Kan_Li ,

Is there an update from the experts yet?

Best regards,
Michael

[Kan_Li · Accepted solution]

Hi @michael_fischer ,

It has been confirmed by the design team, it is IP behavior. If triggered by START bit from SW or Channel Link, there is no minor loop done signal generated.

Have a great day,
Kan

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[michael_fischer]

Hello @Kan_Li ,

>there is no minor loop done signal generated.
I think there is no major loop done signal too.

Best regards,
Michael

[Kan_Li]

Hi @michael_fischer ,

Yes, you are right!

Best Regards,

Kan

[Kan_Li]

Hi @michael_fischer ,

This issue has been submitted to Designer for investigation, and I will let you know when I have any more info from there.

Thanks for your patience!

Have a great day,
Kan

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[michael_fischer]

Hello @Kan_Li ,

Is there an update from the Designer yet?

Best regards,
Michael

[Kan_Li]

Hi @michael_fischer ,

This issue has been reproduced here but the designer is still investigating the root cause, and the expert also recommended reducing the EDMA clock to resolve the low pulse peak issue, but reducing the EMDA clock may lower the performance, you may balance it according to the application requirements.

Have a great day,
Kan

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