i.MX RT1170 : Bug in SDK source code that configures SEMC for SRAM.

[Norihiro]

Hello NXP team, 

I think I found a potential bug in the code which configure SEMC for i.MX RT1170.

Could you review your source code?

Assumption of hardware where this code runs: 

 - Externa SRAM is used

 - Address A8 pin operates as chip select

Here is snippet of code from SEMC_ConfigureSRAMWithChipSelection in "fsl_secm.c" for i.MX RT1170.

Line#777~789

uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ?
(SEMC_IOCR_PSRAM_CE - 1U) :
((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_PSRAM_CE_A8 : SEMC_IOCR_PSRAM_CE);

I think there should be "#if def"  like other part in this function. 

For example, here is code from line#855.

#if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT > 0x01U)
    case kSEMC_SRAM_CS1:
        base->BR9 = tempBRVal;
        break;
    case kSEMC_SRAM_CS2:
        base->BR10 = tempBRVal;
        break;
    case kSEMC_SRAM_CS3:
        base->BR11 = tempBRVal;
        break;
#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */

Otherwise, muxCe is set to wrong setting that is expected for other i.MXRT such as 1060.

Regards,

Norihiro Michigami

AVNET

[VicKrawciw]

So - has this been fixed yet? I just hit it today after several hours wondering why my 2 CS pins were not operating correctly. I downloaded the SDK recently and fsl_semc.c is still dated 2020.

[jingpan · Accepted solution]

Hi @Norihiro ,

Yes, you are correct. This code is for RT1060 but not fit for RT1170. Their registers are different here. I'll report this error.

Best regards,

Jing

[Norihiro]

Hello Jing, 

Thank you for checking this report. 

I understand that NXP keeps fixing known bugs on SDK. 

Can I find any notification once this error gets fixed by

NXP through release note of SDK or this thread? 

Regards,

Norihiro Michigami

AVNET

[jingpan]

Hi @Norihiro ,

Yes, this bug will be fixed in next release. It will be note in release note.

Regards,

Jing