Hi All
I note that the eDMA support for linking to other DMA channels (to trigger them on completion of a first DMA operation) doesn't support triggering on both the minor loop and the major loop.
The channel link types that it supports are:
/*! @brief Channel link type */
typedef enum _edma_channel_link_type
{
kEDMA_LinkNone = 0x0U, /*!< No channel link */
kEDMA_MinorLink, /*!< Channel link after each minor loop */
kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */
} edma_channel_link_type_t;
In some cases it is necessary to be able to trigger on both loop completions and so I tested a modification in order to do this (eg. adding a further enum for kEDMA_Major_andMinorLink) to verify that there is no restriction in the HW.
My test case is below.
1. I configure a DMA channel to write to a port toggle register so that I can see each time it takes place (as a GPIO is toggled by it). This is DMA channel 1.
2. Using a UART driver that uses DMA for transmission I add a link to channel 1 on both minor and major loops at the same time.
The UART is used as a CLI and so will echo back characters and print out a help screen when "help" is entered.
3. Here is the result of the above (when both major and minor loops are enabled).
a. When I type in "help<cr>" I get this for the 'h' (and equivalent for the further letters)
The botton line is the UART TX line, showing the 'h' being echoed.
The top line shows the port being toggled by DMA channel 1 activity, which was triggered when the UART Tx DMA completed (this copied just the single byte as DMA transfer due to the UART's TX trigger being set). It shows therefore where the UART DMA took place.
It is to be noted that a single byte transfer was set up and so the main loop linked trigger to channel 1 caused the port toggle. If a minor loop trigger only is configured there is no chained DMA trigger as no minor loop is used.
b. When the enter key is pressed there is a menu displayed and so more activity:
Note that initially there are two faster UART DMA transfers (to fill up the LPUART HW buffer) and then one transfer each UART byte period as the next byte needs to be prepared. This is visible as the UART DMA loop (this time minor loop [single character transfers] as multiple byte are configured) triggers channel 1 DMA, causing the GPIO port toggle.
c. At the end of this transfer it is seen how the DMA has completed before the last two bytes (in UART HW Tx buffer) are completely sent. The chained DMA channel's operation allows this to be visualised well.
Note that if the major loop trigger is not enabled the last GPIO change is missing.
If minor loop chaining is not enabled only the last GPIO change takes place.
As seen above, if not both minor and major loop termination are used at the same time some of the linked triggers will not take place and so the functionality is not complete. This therefore shows that an extension to the eDMA linking support can be useful in such circumstances.
Regards
Mark
