Why does Boot-ROM not set command interval?

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Why does Boot-ROM not set command interval?

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imxrtuser
Senior Contributor I

Hello,

if I specify a command interval in my XIP device configuration block the CSINTERVALUNIT bit in flash register FLSHCR1A1 will not be set to the value I specified.

pastedImage_1.png

Why does the Boot-ROM not set the value I specify? Does it not support this?

Kind regards,

Stefan

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jeremyzhou
NXP Employee
NXP Employee

Hi Stefan Mitterhauser ,

Thanks for your reply.
The commandInterval is only used to configure the SPI NAND currently as aforementioned.
In addition, the CSINTERVAL is used to set the minimum interval between flash device Chip selection deassertion and flash
device Chip selection assertion, and we can find that it's nothing along with the command interval actually.
Hope this is clear.

pastedImage_1.png

Have a great day,
TIC

 

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jeremyzhou
NXP Employee
NXP Employee

Hi Stefan Mitterhauser ,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) Why does the Boot-ROM not set the value I specify? Does it not support this?
-- According to the below figure, the interval would be 2 cycles actually which is consistent with the configuration in qspiflash_config struct.

pastedImage_1.png

Have a great day,
TIC

 

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imxrtuser
Senior Contributor I

Hi jeremy,

you are right. In this case it does not matter.


I tested it with the flexspi_nor_polling_transfer example project for RT1020 and set the value to

.commandInterval  = 8u,

but the register value CSINTERVALUNIT does not get set to 8.

Kind regards,

Stefan

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jeremyzhou
NXP Employee
NXP Employee

Hi Stefan Mitterhauser ,

Thanks for your reply.
The commandInterval is only used to configure the SPI NAND currently as aforementioned.
In addition, the CSINTERVAL is used to set the minimum interval between flash device Chip selection deassertion and flash
device Chip selection assertion, and we can find that it's nothing along with the command interval actually.
Hope this is clear.

pastedImage_1.png

Have a great day,
TIC

 

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imxrtuser
Senior Contributor I

Thank you Jeremy!

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jeremyzhou
NXP Employee
NXP Employee

Hi Stefan Mitterhauser ,

Sorry for reply late.
After reviewing the RM, I find that commandInterval is invalid for Serial (SPI) NOR actually, currently, it is used for SPI NAND only at high frequency.

pastedImage_2.png

Have a great day,
TIC

 

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imxrtuser
Senior Contributor I

Hey Jeremy,

what does the FlexSPI do to avoid timing problems with NOR flash?

The sentence from the Reference Manual is not clear to me. For me it could mean that the commandInterval value is used for every flash but for NAND flash it is only used if it is operated at high frequencies.

Or it could mean it is used for NAND flash if it is operated at high frequency and for no other flash at all.

Kind regards,

Stefan

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