Using SDRAM for large data on imxRT1050 EVKB

[rajtend]

Hi,

I am using iMXRT1050 EVKB.
I have an application which has large data arrays.
I cannot allocate them over heap or stack as the size is quite small.

When I tried to allocate the arrays in NCACHE region, then the application compiles.
However I get hard fault accessing the region.
How to solve this problem?

AT_NONCACHEABLE_SECTION_ALIGN(double arrA[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrA1[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(double arrB[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrB1[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(double arrC[200], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrC1[200], 8);
AT_NONCACHEABLE_SECTION_ALIGN(double arrD[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrD1[100], 8);

Linker configuration:

Hard fault:

[EdwinHz]

Hi @rajtend,

Please make sure you follow the steps listed on the following blog post: Placing Code in Sections with managed GNU Linker Scripts | MCU on Eclipse

BR,
Edwin. 

[rajtend]

I have followed the steps, however the hard fault doesn't go away.

[EdwinHz]

Hi @rajtend,

How are you accessing the arrays? Are I tried to recreate the issue, but I am not able to; it works OK for me. I have the following arrays as global variables:

AT_NONCACHEABLE_SECTION_ALIGN(double arrA[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrA1[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(double arrB[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrB1[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(double arrC[200], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrC1[200], 8);
AT_NONCACHEABLE_SECTION_ALIGN(double arrD[100], 8);
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t arrD1[100], 8);

And under main, I set a value of 8 to all of them at their last position:

    arrA[100] = 8;
    arrA1[100] = 8;
    arrB[100] = 8;
    arrB1[100] = 8;
    arrC[200] = 8;
    arrC1[200] = 8;
    arrD[100] = 8;
    arrD1[100] = 8;

This results in no compilation error or hard fault either.

Take a look into the following community post: Solved: Re: Imprecise Bus Error when trying to make use of SDRAM on RT1020 EVK - NXP Community

As well as the following application note (specifically section "4.3.2. Use non-cacheable buffers"): Using the i.MXRT L1 Cache

BR,
Edwin.

[rajtend]

Can you please tell me?
1. What is the starting address for SDRAM for imx RT1050 evkb? where can i find it?
2. What does the following code means? I saw it asserted in one time while running.
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(nonCacheStart % size));
assert(size == (uint32_t)(1 << i));

[EdwinHz]

Hi @rajtend,

The available size for the RT1050 can be found on its Reference Manual, specifically on "Table 3-1. System memory map (CM7)":

The code you mention makes sure of two things: The first like asserts that the region base (nonCacheStart) is a multiple of size. The second makes sure that size is no larger than 2^32, since the variable 'i' will have the base-2 order of size due to the previous "while()":

    while ((size >> i) > 0x1U)
    {
        i++;
    }

If the code asserts and breaks at that point, it means that the MPU region size does not comply with the condition where it is a multiple of size, or that it is bigger than 2^32.

BR,
Edwin.

[rajtend]

Hi,

Thanks a lot for the steps.
I am able to make it work. I have added several preprocessor defines:

Can you tell me which are not needed?

[EdwinHz · Accepted solution]

Hi @rajtend,

I'm afraid I wouldn't be able to tell you what preprocessor definitions are not needed, since this depends on your specific application.

I would recommend you compare your project with one in our SDK examples and go from there.

BR,
Edwin.