Testing CM4 core in MIMXRT1176

[ManikantaRobbi]

Hi,

I'm working with RT-1176 custom designed board. I had few queries regarding core CM7/CM4

1)In reference manual, the below block diagram show the peripherals dedicated to CM7 and CM4.

Consider LPI2C5 belongs to CM4, but I created a project selecting core CM7 and started testing salve connected to  LPI2C5, as per my understanding it belongs to CM4 but why it is working with CM7.

2)When I imported SDK example for CM4 then in Memory Configuration:

"LINK TO RAM" is enabled and memory it is mapping to 0x8000_0000.

why? Is it designed such a way that CM7 only able to access QSPI (0X3000_0000).

And How to Flash Projects belongs to CM4 using J-link(Is the process same as CM7 instead of connecting CM7 we need to Connect--->Device MIMXRT1176XXX_CM4. Awaiting for reply.

Thanks & Regards,

Manikanta Robbi. 

[Masmiseim]

Hello ManikantaRobbi,

• Both cores can access all peripherals. But the access to the dedicated peripherals is faster and does not add load on the crossbar of the other core.
• The Memory mapped access to the external Flash via FlexSPI is available on two address ranges for the M4-Core. 0x0800_0000 is faster for code execution for the M4 core.

Regards

[ManikantaRobbi]

Hi @Masmiseim ,

Thanks for the information. But why we need to perform testing  CM4 using "LINK TO RAM" only in EVK.

Cant we flash to QSPI.

Thanks & Regards,

Manikanta Robbi.

[Masmiseim]

Hello @ManikantaRobbi ,

that depends on how you want to start the M4 core. By default, the M7 core is the master core. This means that only this core starts after the operating voltage is applied. At runtime, the M7 core can then start the M4 core
In the SDK examples, the M4 core is linked to the RAM area. The M7 core then loads the memory area (with code and data) into the RAM and starts the M4 core with the RAM area as the start address.
Alternatively, you can also link the M4 core into the flash; in this case you must ensure that the two images (for the M7 and M4 core) do not overlap, i.e. that they are in separate "partitions". The M4 can then be started with the address of the flash partition (XiP). The start address is then in the 0x3000_0000 range, even if the M4 application is linked to 0x0800_0000.

Best regards

[ManikantaRobbi]

Thanks @Masmiseim ,

This information is useful, I had approached same way creating a new project for CM4 and Disabled "LINK TO RAM"  and changed default mem config. As you mentioned we can use CM4 to flash in 0x30000000 region. Can you elaborate procedure during mem config, I tried many possible case all builds are getting failed.

Thank you. 

[Masmiseim]

How this is done depends on the Development Environment. I guess you are using MCUXpresso, but I’m not familiar with this IDE.

But basically, the configuration should be identical to the one from the M7 core with the exception of the “.boot_xxx” sections. These sections are only necessary on the M4 core.

And of course, the Flash Base-Address must be different to avoid a overlapping of the image from both cores.

For example:

0x30000000 --> M7-Core with one Megabyte Flash-Space

0x30100000 --> M4-Core respectively 0x08100000 

[ManikantaRobbi]

“.boot_xxx” sections. i.e Is it necessary to change the boot switches from internal boot mode. while using cm4 project to use flash memory 0x0800_0000.

[ManikantaRobbi]

Hi @Masmiseim ,

Thanks for the information. I had followed the instructions for mem config. Image attached reflects the changes done in memory "0x30100000"  and the project created for CM4. But again I'm getting build failed.

This is log message after build.

So can't we create a new project for CM4 access the QSPI.

Thanks,

Manikanta Robbi.

[Masmiseim]

Looks to me like a problem with the JTAG connection. Does a connect via J-Link Commander to the M4 core of the iMXRT1170 work?