RT1062 Stalls and Crashes on Read / Write to eLCDIF Config

[CameronKramr]

Running an RT1062 bare-metal on a custom board with some known issues. Code for configuring the eLCDIF works on the EVK board for the RT1062, but when I run the same code on a custom board, writes or reads to LCDIF control registers stall the processor and causes the debugger (Segger J-link) to error out. If I by-pass PLL5 and use the 24 MHz clock directly, the issue persists in the same way. This is enough to trigger the error on my custom board, but not the EVK:

//Never gets past here
uint32_t ctrl = LCDIF->CTRL;

The LCDIF is the only component that fails like this (so far). I have been able to configure the SEMC, ADC, PIT, and GPIO without issue. 

I suspect it's related to the fact that I have to cut the NVCC_PLL trace to the processor due to some design errors and can't otherwise attach the suggested capacitors. Otherwise the 24 MHz Clock starts and is strong/clean.

I've seen similar failures when attempting to edit registers when their clocks are gated, but I've walked the clock tree (manually) several times and it looks good to me.

Because everything else works, I feel like it could be a configuration issue, but because the same code doesn't crash on the EVK, I'm starting to think the issue is hardware related.

Q1: Has anyone else experienced something similar (specific modules not working)?

Q2: Was that was solved by correcting the NVCC_PLL capacitance or something else?

Q3: Are there other troubleshooting tests or things to look at that might shine more light on what's going on?

Trying to get help / suggestions before doing a full re-run of the design.

Here's the clock registers for the by-passed PLL configuration:

ccm                    <struct>      
    CCR                0x0401107f    
    CSR                0x00000038    
    CCSR               0x00000100    
    CACRR              0x00000001    
    CBCDR              0x38038300    
    CBCMR              0xf42e8104    
    CSCMR1             0x6793007f    
    CSCMR2             0x13192f06    
    CSCDR1             0x06490b03    
    CS1CDR             0x0ec102c1    
    CS2CDR             0x000736c1    
    CDCDR              0x33f71f92    
    CSCDR2             0x00010150    
    CSCDR3             0x00030841    
    CDHIPR             0x00000000    
    CLPCR              0x00000079    
    CISR               0x04d20000    
    CIMR               0xffffffff    
    CCOSR              0x000a0001    
    CGPR               0x0000fe62    
    CCGR0              0xc0c00fff    
    CCGR1              0xcc033000    
    CCGR2              0x3c3f0033    
    CCGR3              0xf00c3c00    
    CCGR4              0x0000f33f    
    CCGR5              0xf0033000    
    CCGR6              0x00fc0fff    
    CCGR7              0xfff00c30    
    CMEOR              0x7fffffff    
ccma                   <struct>      
    PLL_ARM            0x80002064    
    PLL_ARM_SET        0x80002064    
    PLL_ARM_CLR        0x80002064    
    PLL_ARM_TOG        0x80002064    
    PLL_USB1           0x80003000    
    PLL_USB1_SET       0x80003000    
    PLL_USB1_CLR       0x80003000    
    PLL_USB1_TOG       0x80003000    
    PLL_USB2           0x00012000    
    PLL_USB2_SET       0x00012000    
    PLL_USB2_CLR       0x00012000    
    PLL_USB2_TOG       0x00012000    
    PLL_SYS            0x80002001    
    PLL_SYS_SET        0x80002001    
    PLL_SYS_CLR        0x80002001    
    PLL_SYS_TOG        0x80002001    
    PLL_SYS_SS         0x00000000    
    PLL_SYS_NUM        0x00000000    
    PLL_SYS_DENOM      0x00000012    
    PLL_AUDIO          0x00011006    
    PLL_AUDIO_SET      0x00011006    
    PLL_AUDIO_CLR      0x00011006    
    PLL_AUDIO_TOG      0x00011006    
    PLL_AUDIO_NUM      0x05f5e100    
    PLL_AUDIO_DENOM    0x2964619c    
    PLL_VIDEO          0x0011201b    
    PLL_VIDEO_SET      0x0011201b    
    PLL_VIDEO_CLR      0x0011201b    
    PLL_VIDEO_TOG      0x0011201b    
    PLL_VIDEO_NUM      0x05f5e100    
    PLL_VIDEO_DENOM    0x10a24447    
    PLL_ENET           0x00011005    
    PLL_ENET_SET       0x00011005    
    PLL_ENET_CLR       0x00011005    
    PLL_ENET_TOG       0x00011005    
    PFD_480            0x0f1a234c    
    PFD_480_SET        0x0f1a234c    
    PFD_480_CLR        0x0f1a234c    
    PFD_480_TOG        0x0f1a234c    
    PFD_528            0x405d4040    
    PFD_528_SET        0x405d4040    
    PFD_528_CLR        0x405d4040    
    PFD_528_TOG        0x405d4040    
    MISC0              0x24008080    
    MISC0_SET          0x24008080    
    MISC0_CLR          0x24008080    
    MISC0_TOG          0x24008080    
    MISC1              0x80030000    
    MISC1_SET          0x80030000    
    MISC1_CLR          0x80030000    
    MISC1_TOG          0x80030000    
    MISC2              0x002f272f    
    MISC2_SET          0x002f272f    
    MISC2_CLR          0x002f272f    
    MISC2_TOG          0x002f272f    

[Gavin_Jia]

Hi @CameronKramr ,

Thanks for your interest in NXP MIMXRT series!

Based on the values you provided for the `CSCDR2` register, the LCDIF pre-clock is still routed through the PLL5 path. The NVCC_PLL capacitor you mentioned is a potential issue; we recommend following the hardware development manual.

Best regards,
Gavin

[CameronKramr]

Hi Gavin,

Thanks for your reply. I thought by configuring by-pass mode in the PLL, it shouldn't matter that I still "used" PLL5. Thanks for the recommendation though.

Anyway, I tried it using PLL2 and still have the same issue. Here's my clock configuration showing that::

ccm                    <struct>      
    CCR                0x0401107f    
    CSR                0x00000038    
    CCSR               0x00000100    
    CACRR              0x00000001    
    CBCDR              0x38038300    
    CBCMR              0xf52e8104    
    CSCMR1             0x6793007f    
    CSCMR2             0x13192f06    
    CSCDR1             0x06490b03    
    CS1CDR             0x0ec102c1    
    CS2CDR             0x000736c1    
    CDCDR              0x33f71f92    
    CSCDR2             0x001c7150    
    CSCDR3             0x00030841    
    CDHIPR             0x00000000    
    CLPCR              0x00000079    
    CISR               0x04d20000    
    CIMR               0xffffffff    
    CCOSR              0x000a0001    
    CGPR               0x0000fe62    
    CCGR0              0xc0c00fff    
    CCGR1              0xcc033000    
    CCGR2              0x3c3f00f3    
    CCGR3              0xf00c3c00    
    CCGR4              0x0000f33f    
    CCGR5              0xf0033000    
    CCGR6              0x00fc0fff    
    CCGR7              0xfff00c30    
    CMEOR              0x7fffffff    
ccma                   <struct>      
    PLL_ARM            0x80002064    
    PLL_ARM_SET        0x80002064    
    PLL_ARM_CLR        0x80002064    
    PLL_ARM_TOG        0x80002064    
    PLL_USB1           0x80003000    
    PLL_USB1_SET       0x80003000    
    PLL_USB1_CLR       0x80003000    
    PLL_USB1_TOG       0x80003000    
    PLL_USB2           0x00012000    
    PLL_USB2_SET       0x00012000    
    PLL_USB2_CLR       0x00012000    
    PLL_USB2_TOG       0x00012000    
    PLL_SYS            0x80002001    
    PLL_SYS_SET        0x80002001    
    PLL_SYS_CLR        0x80002001    
    PLL_SYS_TOG        0x80002001    
    PLL_SYS_SS         0x00000000    
    PLL_SYS_NUM        0x00000000    
    PLL_SYS_DENOM      0x00000012    
    PLL_AUDIO          0x00011006    
    PLL_AUDIO_SET      0x00011006    
    PLL_AUDIO_CLR      0x00011006    
    PLL_AUDIO_TOG      0x00011006    
    PLL_AUDIO_NUM      0x05f5e100    
    PLL_AUDIO_DENOM    0x2964619c    
    PLL_VIDEO          0x0001100c    
    PLL_VIDEO_SET      0x0001100c    
    PLL_VIDEO_CLR      0x0001100c    
    PLL_VIDEO_TOG      0x0001100c    
    PLL_VIDEO_NUM      0x05f5e100    
    PLL_VIDEO_DENOM    0x10a24447    
    PLL_ENET           0x00011005    
    PLL_ENET_SET       0x00011005    
    PLL_ENET_CLR       0x00011005    
    PLL_ENET_TOG       0x00011005    
    PFD_480            0x0f1a234c    
    PFD_480_SET        0x0f1a234c    
    PFD_480_CLR        0x0f1a234c    
    PFD_480_TOG        0x0f1a234c    
    PFD_528            0x405d4040    
    PFD_528_SET        0x405d4040    
    PFD_528_CLR        0x405d4040    
    PFD_528_TOG        0x405d4040    
    MISC0              0x24008080    
    MISC0_SET          0x24008080    
    MISC0_CLR          0x24008080    
    MISC0_TOG          0x24008080    
    MISC1              0x80030000    
    MISC1_SET          0x80030000    
    MISC1_CLR          0x80030000    
    MISC1_TOG          0x80030000    
    MISC2              0x002f272f    
    MISC2_SET          0x002f272f    
    MISC2_CLR          0x002f272f    
    MISC2_TOG          0x002f272f    

Please let me know if anything else would help debug the issue. I have new boards that will have the NVCC_PLL capacitors so I'll be able to test with that. I just think it's strange that the LCDIF appears to be the only module affected. Thanks again for your help!