MIMXRT685-EVK codec WM8904 adc problem

[slawek_zabielsk]

Hi. I work on the MIMXRT685-EVK devboard. The problem is with codec WM8904. The configuration of audio track is compatible with example from SDK_2.8.0_EVK-MIMXRT685 (I2S\dma_record_playback). Bit rate 16-bits, 2-channels, sample rate 48kHz. RxDMA and TxDMA work simultaneously. Callback DMA functions are activated. I will use mechanism of 3 buffers 128sample each, described in AN12749. Everything seems to work without problems. I can even see the correct waveform on the oscilloscope. (I give a triangular waveform on input with amplitude 1.41Vpp@375Hz, on output is the same).
see the waveform file - NewFile1_141020.png
However, when I look through the data in the buffer, the waveform is strange. (see the Excel sheet file: test_func2.xlsx, 16_bit_375Hz_1.41Vpp.png) They are not like those on the oscilloscope. This indicates a problem with the ADC converter. The input attenuation of the ADC converter is set to 0dB. The input works in single-ended mode. The PGA amplifier is switched on before ADC converter. Its gain is set to 0dB. I have set the reference voltage to Vmid. I measured the value of codec supply voltage: 1.84Vdc.

Questions:
1) Are the settings for the below mentioned parameters correct?
2) Is the assumption that the transducer gives int16 numbers with a sign in DMA buffer correct?
3) Is the assumption that in the buffer a more significant byte first appears, then a less significant (big-endian) is correct?
4) Is the assumption that the left side sample first appears in the buffer, then the right one, correct?
5) Another decrease of the ADC converter's attenuation causes the number of wraps of the triangular waveform to decrease. (I checked for 0dB, -10dB, -20dB, -60dB) For -60dB the waveform was already clear. Why is it so. Why can't I see the correct waveform for 0dB?

My configuration:
wm8904_config_t wm8904Config = {
.i2cConfig = {.codecI2CInstance = BOARD_CODEC_I2C_INSTANCE},
.recordSource = kWM8904_RecordSourceLineInput,
.recordChannelLeft = kWM8904_RecordChannelLeft2,
.recordChannelRight = kWM8904_RecordChannelRight2,
.playSource = kWM8904_PlaySourceDAC,
.slaveAddress = WM8904_I2C_ADDRESS,
.protocol = kWM8904_ProtocolI2S,
.format = {.sampleRate = kWM8904_SampleRate48kHz, .bitWidth = kWM8904_BitWidth16},
.master = false,
};
codec_config_t boardCodecConfig = {.codecDevType = kCODEC_WM8904, .codecDevConfig = &wm8904Config};

#define DSP_I2S_CLOCK_DIVIDER 16

#define DSP_I2S_TX_MODE kI2S_MasterSlaveNormalSlave
#define DSP_I2S_RX_MODE kI2S_MasterSlaveNormalMaster

/*
* masterSlave = kI2S_MasterSlaveNormalMaster;
* mode = kI2S_ModeI2sClassic;
* rightLow = false;
* leftJust = false;
* pdmData = false;
* sckPol = false;
* wsPol = false;
* divider = 1;
* oneChannel = false;
* dataLength = 16;
* frameLength = 32;
* position = 0;
* watermark = 4;
* txEmptyZero = true;
* pack48 = false;
*/
I2S_TxGetDefaultConfig(&s_TxConfig);
s_TxConfig.divider = DSP_I2S_CLOCK_DIVIDER;
s_TxConfig.masterSlave = DSP_I2S_TX_MODE;

/*
* masterSlave = kI2S_MasterSlaveNormalSlave;
* mode = kI2S_ModeI2sClassic;
* rightLow = false;
* leftJust = false;
* pdmData = false;
* sckPol = false;
* wsPol = false;
* divider = 1;
* oneChannel = false;
* dataLength = 16;
* frameLength = 32;
* position = 0;
* watermark = 4;
* txEmptyZero = false;
* pack48 = false;
*/
I2S_RxGetDefaultConfig(&s_RxConfig);
s_RxConfig.divider = DSP_I2S_CLOCK_DIVIDER;
s_RxConfig.masterSlave = DSP_I2S_RX_MODE;

Don't hesitate to ask a question in case you need further information on my project.

Slawek

[slawek_zabielsk]

Hi again.

I gathered new data concernig my problem. (ADC_problem_0dB_16_bit_375Hz_1.41Vpp.xlsx) It shows better the ADC problem I have than prevoius XLSX file.

Slawek

[FelipeGarcia]

Hi Slawek,

Please see my answers below.

1. For what I could see you did not modify the SDK example, is that correct? Parameters should be correct.

2. From the example code DMA buffer is 8 bit unsigned so the 16 bits of data will be two immediate DMA buffers, one after the other.

3. This is configured with the LEFTJUST configuration bit.

4. The order of left and right data is selectable via the RIGHTLOW configuration bit.

5. Do you mean that when working at -60 DB the signal is correct? Could you please share this?

Best regards,

Felipe

[slawek_zabielsk · Accepted solution]

Hi,

I've already found a solution on this problem. There was some small mistake in code made by me when testing the devboard. Thank you for your assitance.