Dear Jing,
thank you for your reply.
I'm using MCUXpresso Config Tools Pins version 13 and Peripheral Version 12.0. The SDK in in version 2.13.1.
Yesterday I did some tests with the MCUXpresso IDE and I can confirm that the Channel number conformed with your one. But also in this tool I have the same problem.
I have discovered that the warning appears as soon as in the Peripheral Signals of the Pins tool I enable OTG1_ID on pin GPIO_AD_09. The funny thing is that when I rout pin OTG1_ID on pin GPIO_AD_09, the LPADC1 peripheral generate the warning for every conversion command that involve the B part of the ADC. (e.g. Channel sample mode = Single end mode, using B and Channel number=B, 1_0 » [T17] USB_OTG2_PWR/WL_DEV_WAKE/U354[10]/J10[2] or B, 1_2 » [P16] USB_OTG1_OC/U26[A2]/J26[4] or B, 1_3 » [L12] SPDIF_SR_CLK/ANATOP_32K_OUT/J26[8] etc....
I'm starting to think there is a bug in this part of the tool. The generated code per the pin mux looks correct to me (see below).
What's your opinion?
Kind regards,
Massimo
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05, /* GPIO_AD_06 is configured as GPIO_MUX3_IO05 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06, /* GPIO_AD_07 is configured as GPIO_MUX3_IO06 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID, /* GPIO_AD_09 is configured as USBPHY1_OTG_ID */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */
0x02U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: high drive strength
Pull / Keep Select Field: Pull Disable, Highz
Pull Up / Down Config. Field: Weak pull down
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */
0x02U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: high drive strength
Pull / Keep Select Field: Pull Disable, Highz
Pull Up / Down Config. Field: Weak pull down
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
}
