Inquiries regarding RT1052 RTC (SNVS)

[Jimmy_Rabbit]

We are developing an EV station using RT1052. We want to use the RTC (SNVS)function in case of shutdown situation.
During communication with EV station and server, EV station (RT1052) stores history and time information using the RTC function when shutdown, and if the power is restored, it should be reconnected to the server so that there should be no problem with time information and history.
I would like to ask you as below, so please reply.

Q1. The exact role of the RTC function and the scenario of history storage operation when supplying emergency power

Q2. As far as I know, history is currently written and stored in SFLASH, but does information be stored in SFLASH when the entire shutdown?
Or whether that information is stored and managed in the Secure Non-Volatile Storage (SNVS) in the MCU

Q3. The current operation scenario in the reference circuit diagram is a structure in which the wake-up voltage 3.3V is normally supplied and woken up,
It is a structure in which power is supplied to the coin cell or supercap when it is shut off in case of emergency.
When emergency power is supplied to the SNVS area, is the history information stored in conjunction with SFLASH? Or is it stored in the SNVS area only

[Jimmy_Rabbit]

Problem solved, thank you for your help.

[EdwinHz]

Hello @Jimmy_Rabbit,

I believe there might be some misconceptions about the features of the SNVS module on the RT1050. The SNVS module is an isolated subsystem inside our i.MX RT family that provides a set of security related features for the chip as a whole. These features are described on Section 7.4 of the Reference Manual, but are not really relevant to this inquiry.

It also provides a set of non-security features, described on section 20.2:

• Realtime Counter (RTC).
• Periodic Interrupts.
• General Purpose Registers.
• Chip power-on/power-off.

When the i.MX RT enters SNVS power domain, only the SNVS module is active, and the rest of the chip is completely powered OFF.

Consequently, the module's features alone are not enough to provide the RT1050 with a memory write mechanism to flash since the rest of the chip (including the memory buses, peripherals, clocks, etc.) are OFF.

Also, it is worth noting that the SNVS_HP domain's RTC is different from the SNVS_LP SRTC. HP's RTC is not active when the chip is powered down, while the SRTC is powered by the coin cell battery, meaning its power source is uninterrupted and can always run regardless of the power state of the i.MX RT.

The RT11xx series adds a SNVS_SRAM to the list of its SNVS features, which allows for an optional bank for memory access when on SNVS domain. After transitioning out of SNVS power domain, the user could store this SRAM contents on flash.

On the RT10xx series, however, this feature is not present. This means that in order to achieve flash writes, you would require to transition out of the SNVS altogether.

I hope this clears things up.

BR,
Edwin.