IMXRT1062 LPSPI problem with delayed sck - CFGR1[sample] = 1

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IMXRT1062 LPSPI problem with delayed sck - CFGR1[sample] = 1

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Kalimanni
Contributor II

Hello,

without setting the sample bit in cfgr1 the lpspi4 works in master mode as aspected. With the sample bit in cfgr1 set for the delayed sck for thr sdi the lpspi4 is not transferring anything. The transfer is not starting.

In the attachment is the modified source from the  evkmimxrt1060_lpspi_edma_b2b_transfer_master example.

What can be the problem that the lpspi4 with activated sample bit in cfgr1 is no more working?Does a clock component need to be activated in addition to the clock for lpspi4 in order to use the delayed sck feature?

Thanks for an answer

kalimann

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Kalimanni
Contributor II
Hello Habib,

i have found a solution. For the sck pin software input on field (SION) must be set to 1.
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LPSPI4_SCK, 1U);

BR
kalimanni

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Kalimanni
Contributor II
Does anyone have any idea why the SPI transmission does not work when the sample bit is set, even though it is only supposed to make the Sck signal fed back via a gate available for reading the input data (MISO).
I have an LED on Sck. If the bit is not set, you can see the LED short glow faintly during transmission.
If the sample bit is set, the LED lights up at full brightness and stays on -> no transmission. Why is the Sck signal only present on the 1st edge and then remains in this state?

kalimanni
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Habib_MS
NXP Employee
NXP Employee

 

Hello @Kalimanni, 

Sorry for taking a while to get back to you. 
I will verify the code and get back to you with a response as soon as possible.  

Just one question: the code you provided needs the header file called "peripherals.h". In order to support you better, could you share me the code inside the function called "BOARD_InitBootPeripherals"? 

BR 
Habib. 

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Kalimanni
Contributor II

Hello Habib_MS,
Thank you very much for your answer.
I have zipped the whole project and attached it. It is adapted for Teensy 4.1. But that only affects the linker script. All the required sources should be there. The files peripherals.h and peripherals.c should be found in the board subdirectory.

BR
kalimanni.

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Kalimanni
Contributor II
Hello Habib,

Have you been able to test the lpspi master yet?
Does the problem also occur for you if the sample bit is set?

BR
kalimanni
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Habib_MS
NXP Employee
NXP Employee

Hello again @Kalimanni. Sorry for taking a while to get back to you.

I am still checking the code, however in order to support you better, can you provide me the next information around your code?

In the project that you provide me the file called "peripherals.c" is empty, is this a mistake?
I did not see in the shared project where the sample bit is configured, can you provide the code section do you configure this bit?
BR,
Habib

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Kalimanni
Contributor II
Hello Habib,

thank you for your answer.
The answer to the first question:
In the project that you provide me the file called "peripherals.c" is empty, is this a mistake?
- No mistake, i have played around with the MCUXpresso Config Tools. I think the config tool has generated this peripherals files. Because i have nothing modified the generated procedures are empty. This files should be not needed but this makes no difference.

The answer to the second question:
I did not see in the shared project where the sample bit is configured, can you provide the code section do you configure this bit?
- In the source directory in the file lpspi_edma_b3b_transfer_master.c in the main function you can find the master configuration.
The sample bit will be set if masterConfig.enableInputDelay is set true in the procedure LPSPI_MasterInit from the lpspi driver file fsl_lpspi.c. The comment characters at the beginning of line 357 must be removed.

/*Master config*/
LPSPI_MasterGetDefaultConfig(&masterConfig);
masterConfig.baudRate = TRANSFER_BAUDRATE;
masterConfig.whichPcs = EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT;
masterConfig.pcsToSckDelayInNanoSec = 1000000000U / (masterConfig.baudRate * 2U);
masterConfig.lastSckToPcsDelayInNanoSec = 1000000000U / (masterConfig.baudRate * 2U);
masterConfig.betweenTransferDelayInNanoSec = 1000000000U / (masterConfig.baudRate * 2U);
// masterConfig.enableInputDelay = true; <== remove the comment characters

srcClock_Hz = LPSPI_MASTER_CLK_FREQ;
LPSPI_MasterInit(EXAMPLE_LPSPI_MASTER_BASEADDR, &masterConfig, srcClock_Hz);

BR,
kalimanni
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Habib_MS
NXP Employee
NXP Employee

Hello again @Kalimanni . Sorry for taking a while to get back to you.

I was able to replicate your issue creating an example code based in your application, I will be working in order to solve it, and I will get back to you with more updates as soon as possible.

BR
Habib.

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Kalimanni
Contributor II
Hello Habib,

Thank you very much for your information. It's good that you were able to reproduce the problem. I'm eagerly awaiting the solution.

BR
kalimanni
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Kalimanni
Contributor II
Hello Habib,

i have found a solution. For the sck pin software input on field (SION) must be set to 1.
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LPSPI4_SCK, 1U);

BR
kalimanni
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