IMXRT: Trailing clocks at end of FlexSPI access?

[neil_weinstock]

The docs for the FlexSPI controller say that the output SPI clock is turned off when the interface is idle.  Timing diagrams, though, show the clock continuing off the right edge of the picture after the end of a transaction.

How many additional clock cycles (if any) can I be guaranteed to get after the transaction is over?  I'm interfacing to an FPGA with no PLL so I'll need those clocks.

Example timing diagram from page 1642 of the i.MX RT1060 Reference Manual:

[Sabina_Bruce]

Hello Neil,

Hope you are doing well.

I am confirming with our team to check if this is a mistake or if in fact there is an expected behavior.

I will update you as soon as I have an answer for you.

Best Regards,

Sabina

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[neil_weinstock]

To add a small additional note: several of the other example timing diagrams, particularly the ones for Hyperflash transfers, do *not* show additional cycles after chip select goes away.  I wonder if it's simply a mistake in the above diagram?

If I *want* some extra clocks after the data transfer I should just be able to add a DUMMY command right before the STOP command in my read and write sequences, right?

[Sabina_Bruce]

Hello Neil,

Hope you are doing well.

I have received confirmation, that this is an error in the diagram. The FlexSPI controller won't toggle the clock signal beyond the negation of the chip select. We've let the documentation team know this needs to be corrected.

Best Regards,

Sabina

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Note: If this post answers your question, please click the Correct Answer button. Thank you!

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