IMX RT1170 EVKB - How to configure XRDC2 domain assignment for an eDMA Bus Master

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IMX RT1170 EVKB - How to configure XRDC2 domain assignment for an eDMA Bus Master

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mneroda
Contributor II

Dear NXP Support Team,

I am configuring the XRDC2 to block the eDMA from making transfers to a specific memory region. I manage to do that by doing this :

    xrdc2_master_domain_assignment_t assignment;

    XRDC2_GetDefaultMasterDomainAssignment(&assignment);

    /* Defining privileges to the eDMA */
    assignment.lock          = false;
    assignment.privilegeAttr = kXRDC2_ForcePrivilege;
    assignment.secureAttr    = kXRDC2_ForceNonSecure;
    assignment.domainId      = 3;

    /* Forcing to apply the policy to all eDMA transactions */
    assignment.mask = 0xFFFFFFFFU;
    assignment.match = 0x00000000U;
    XRDC2_SetMasterDomainAssignment(DEMO_XRDC2, kXRDC2_Master_M7_EDMA, 0,        &assignment);
 

The problem is that by setting MASK = 0xFFFFFFFFU and MATCH = 0x00000000U a hit is generated for all the eDMA transfers.

I would like to know how I can fine tune the MASK/MATCH fields.

Thanks !

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mayliu1
NXP Employee
NXP Employee

Hi @mneroda ,

Thanks for your updated information.

I check the IMXRT1170RM, I find the following table.

mayliu1_0-1754895716315.png

mayliu1_1-1754895774052.png

Wish it helps you.

Best Regards

MayLiu

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mayliu1
NXP Employee
NXP Employee

Hi @mneroda ,

Thank you so much for your interest in our products and for using our community.

In order to better support your question, please provide more detailed information about your requirements.

What do you mean "configuring the XRDC2 to block the eDMA from making transfers to a specific memory region".

By the way, I suggest you can refer to the following SDK API link.

 MCUXpresso SDK API Reference Manual: XRDC: Extended Resource Domain Controller


Best Regards
MayLiu

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mneroda
Contributor II

Hi @mayliu1,

Thanks a lot for your answer.

Let me clarify what I’m trying to do.

I’m working on the i.MX RT1170 and using the XRDC2 peripheral to enforce memory access control between cores and peripherals. My goal is to block eDMA (DMA0) from writing to a specific memory region that has been protected by an XRDC2 memory region descriptor.<

I hope it clarifies a bit what I am trying to do.

Best regards,
Mickaël

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mayliu1
NXP Employee
NXP Employee

Hi @mneroda ,

Thanks for your updated information.

I check the IMXRT1170RM, I find the following table.

mayliu1_0-1754895716315.png

mayliu1_1-1754895774052.png

Wish it helps you.

Best Regards

MayLiu

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