HyperFLASH + HyperRAM on IMXRT1060

[pjanco]

Hi,

I need to use alot of GPIO in my future design. So, I would like to replace SDRAM memory with HYPERRAM memory. I need to verify if my ideas about my future design are correct.

IMXRT1060 have two FLEXSPI interfaces:

HyperFLASH memory S26KS512S will be connected to FLEXSPI interface in Octal mode. This memory will be used for system BOOT. This is the same connection as used in reference design MIMXRT1060 - EVK.

HyperRAM memory will be connected to FLEXSPI2 interface in Octal mode.

And optionally I want to connect small nonvolatile FRAM memory to FLEXSPI2 interface in Quad mode.

I want to use HyperRAM as buffer for CSI camera and small FRAM for power-safe write cache for writing data into SD card.

It is possible to connect HyperRAM in Octal mode and FRAM in Quad mode to the same interface at the same time?

What system speed can I expect from this configuration? Will it be simillar to SDRAM speed?

Regards,

Peter.

[art]

Q. It is possible to connect HyperRAM in Octal mode and FRAM in Quad mode to the same interface at the same time?

A. Yes, it is possible. You have to use different Chip Select signals for different devices. Also, you have to appropriately configure the LUTs for each device.

Q. What system speed can I expect from this configuration? Will it be simillar to SDRAM speed?

A. The system performance with HyperRAM will be roughly similar to the one with SDRAM.

Have a great day,
Artur

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[pjanco]

Hi,

thanks for answer.

Are you sure about combination of FRAM + HypeRAM on the same interface?

I am worried about different supported frequencies for this two chips. HyperRAM support 166Mhz and FRAM support only 108Mhz. Does this mean I have to use both chips at the same lower frequency? Or can I use one of them at 166Mhz and other at 100Mhz?

I am also trying to write data to HyperFLASH. My code is running from HyperFLASH and few functions responsible for writing are located in SRAM_ITC. I am using default "FlexSPI Configuration Block" from file "evkbimxrt1050_flexspi_nor_config.c" provided by SDK.

In this file, clock is configured to 133Mhz and it is working well for reading from flash. But if I try to write at this speed, there is about 1/3 of writed data different then it should be. If I change clock to 80Mhz, it is working well also for writing. I do not understand why I have problem with writing at higher frequencies if reading is working well. In configuration block is one parameter named "dataValidTime". According to description, there is some diffrent behavior related to this parameter if clock is less then 100Mhz and bigger then 100Mhz.

Do you know something more about writing to HyperFLASH?

[art]

Q. Are you sure about combination of FRAM + HypeRAM on the same interface?

A. Yes, you can use HyperRAM and QSPI FRAM devices on the same interface, using different chip selects.

Q. Does this mean I have to use both chips at the same lower frequency?

A. Typically, yes, you have to use the same frequency for both devices, connected to the same FlexSPI interface. However, if the FRAM accesses are relatively rare, you can stop the HyperRAM access, then configure the flash clock to the lower frequency (e.g. half the clock frequency by setting the MCR0[HSEN] bit, this is the fastest way to lower the clock frequency) then access the FRAM and then switch the flash clock back to higher frequency.

Q. I do not understand why I have problem with writing at higher frequencies if reading is working well.

A. It seems to be some chip-specific timing related. Also, please note that if you boot and XiP from a HyperFlash device, only the Read path LUT sequences become initialized at boot time, the Write path LUT sequences should be initialized manually further.

Best Regards,
Artur