FLEXSPI Root Clock vs QSPI Bus Speed

[mjpovi]

Hi,

I've set a FLEXSPI to be clocked at 99 Mhz, using the PLL2_PFD2 (396 Mhz), so I'm expecting to get a 99 MHz bus clock using a clock divider of 4, or a 132 MHz bus clock with a divider of 3, but instead I seem to be getting either about 12 MHz to 16 MHz on the SPI SCLK line for a QSPI fast read.   What could I be missing here ?  I've checked my register settings to double check that the mux and divider settings to the FLEXSPI block are valid.  I am using the FLEXSPI blocking read function to perform the transfer with  NOR Flash device

[mjpovi]

Hi:
[[ For the 132 MHz setting ]]
(gdb) p/x *(uint32_t*)0x400fC01C
$2 = 0x45100001
(gdb) p/x *(uint32_t*)0x400d8100
$3 = 0x5058505b

Thanks again very much, I discovered that I was probing the incorrect test point and so I am now able to observe the correct FLEXSPI SCLK frequency / waveform on the bus, as expected per the clock setting(s).
  
I have a follow-up question, which is, for the QSPI bus pin(s) am I able to set the drive-strength/output-impedance and if yes, could you point me to the ref. manual or how to do this ?  
Thanks again !

[jeremyzhou · Accepted solution]

Hi @mjpovi ,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) For the QSPI bus pin(s) am I able to set the drive-strength/output-impedance and if yes, could you point me to the ref. manual or how to do this?
-- Yes, you can do it, for instance, you can configure the FlexSPI's pins in the BOARD_InitPins as below shows.

void BOARD_InitPins(void) {
  CLOCK_EnableClock(kCLOCK_Iomuxc);           

  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 1U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 1U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 1U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 1U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 1U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 1U); 
  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 1U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0x10F1U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0x10F1U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0x10F1U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0x10F1U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0x10F1U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0x10F1U); 
  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0x10F1U); 
}

Have a great day,
TIC

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[jay_heng]

You can search IOMUXC_SetPinConfig() function in fsl_iomuxc.c or IOMUXC_SW_PAD_CTL_PAD_xxPinName register description in RM

[jay_heng]

What you mean is FlexSPI1 instance, right?

From your attached clock_config.c, it seems to be ok.

Sys_PLL = 528MHz

PLL2_PFD2 = (528 * 18) / 24 = 396MHz

FlexSPI1 Clock = 396 / 4 = 99MHz.

Can you please dump below two registers to double check?

CCM_CSCMR1 - 0x400F_C01C

CCM_ANALOG_PFD_528 - 0x400D_8100