Dual-core Issue: Cortex-M7 stable, but Cortex-M4 hangs during Ethernet communication (Whitebeet/Codi

[techexplorer_139]

Hi everyone,

We are developing a dual-core application using an [IMXRT-1176-EVKB] and a Whitebeet Codico board for Ethernet communication.

We’ve hit a specific bottleneck: our firmware runs perfectly when executed on the Cortex-M7 core. However, when we run the same logic on the Cortex-M4 core, the application works for a short duration before hanging. This hang eventually leads to an array buffer overflow on the node side.

A few details on our troubleshooting:

Clocks: We have verified the clock configurations. Since we do achieve partial/initial communication on the CM4, we’ve ruled out a basic clock setup error.

Symptom: The hang is inconsistent in timing but consistent in result—stalling the communication flow and overflowing the node's buffers.

Has anyone encountered performance or timing discrepancies between the CM7 and CM4 when interfacing with the Whitebeet module? 

Any insights or suggestions on where to look next would be greatly appreciated!

[Kan_Li]

Hi @techexplorer_139 ，

When you run the application on M4, did M7 have some code to run as well? and where did you place the data section of M4, somewhere shared by M7 and M4 or just owned by M4? Have you increased the optimization option for the M4 code? Does it make any difference?  Please kindly clarify.

Have a great day,
Kan

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[techexplorer_139]

When i run the application on CM4, the CM7 has only small code that starts the booting of CM4 as given in the helloworld_cm7 example.

For the data section placement i have shared the screenshots of memory map and linker GUI.

Currently we are working on the optimisation of code of CM4 to make it run as in CM7.

[Kan_Li]

Hi @techexplorer_139 ,

Thanks for the info! I noticed you have the M4 code running in SDRAM, but is it possible to relocate to SRAM for M4 only? That would increase the performance a lot.

Have a great day,
Kan

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[techexplorer_139]

Yes, we tried to move different RAM section like OCRAM, SRAM_ITC_cm4, DTCM, etc. but when we build the code, it overflows that section minimum by 250% and the size is ~505KB.

[Kan_Li]

Hi @techexplorer_139 ,

How about running the M4 code in flash and allocate the data section in RAM space such as SRAM_ITC_cm4?

Have a great day,
Kan

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[techexplorer_139]

I tried running as your suggesstion and CM7 core boots up but CM4 core doesnt halt in the main and the code is giving the error as mentioned in the screenshot. I have also changed the boot address of CM4 as board_flash address in CM7 main function.

[Kan_Li]

Hi @techexplorer_139 ,.

We provide a doc regarding how to run slave core project as a XIP target, please kindly refer to https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs-Knowledge/RT1170-How-to-make-a-slave-core-projec... for details.

Hope that helps,

Have a great day,
Kan

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[techexplorer_139]

I tried as given in the link but now it didnt boot the second core.

[Kan_Li]

Hi @techexplorer_139 ,

Have you tried only relocating the data section into SRAM for M4?  Did it make any difference?

Have a great day,
Kan

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[techexplorer_139]

Yes, I tried moving the data section to various parts of SRAM such as SRAM_OC, SRAM_ITC_cm4, SRAM_DTCM, but the only difference was the usage was overflown in all the parts.