Cannot connect P&E MultiLink to MIMXRT1064: "Warning: Unable to go to background. Core is running"

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Cannot connect P&E MultiLink to MIMXRT1064: "Warning: Unable to go to background. Core is running"

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jlzm
Contributor II

We are unable to connect from a MultiLink to the SWD interface of an i.MX RT1064 on a custom board design. The board is new and nothing has been loaded into the RT1064. Both blue and yellow LEDs on the MultiLink are on when plugged into the RT1064's SWD port and there is clock and data traffic on the SWD pins when trying to connect. We have also probed the RT1064 and verified that there is correct voltage on power rails and that its 24 MHz oscillator is running. We get the following warning repeated several times in P&E PROGACMP before it fails. We also cannot connect using MCUXpresso.

"Warning: Unable to go to background. Core is running"

We are pretty sure this is a hardware issue specific to this custom design. We have other custom RT1064 board designs that we can connect to using the same MultiLink unit. However, we are having trouble finding the cause of this.

Any ideas on what else we can check?

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jlzm
Contributor II

Hi @mayliu1 

Problem solved. The hardware issue was resolved by using a different debugger tool.

Marking this as resolved. Thank you for your assistance.

Regards,

Jason

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310 次查看
jlzm
Contributor II

Hi @mayliu1 

Problem solved. The hardware issue was resolved by using a different debugger tool.

Marking this as resolved. Thank you for your assistance.

Regards,

Jason

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487 次查看
mayliu1
NXP Employee
NXP Employee

Hi @jlzm ,

Thank you so much for your interest in our products and for using our community.

I suggest you check the following points:

1:Please check if the Reset pin is properly pulled low to reset the RT1064 chip, Use an       oscilloscope to confirm the reset pulse duration and stability.

    Please  use an oscilloscope to check whether the SWD signals are stable and normal.

2:   Please try to lower the speed of SWD clock speed? (RT1064 default debug is SWD)

3:   Did you check your BOOT MODE[1:0] pins and BOOT CFG pins setting correctly?

       

Best Regards

MayLiu

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jlzm
Contributor II

Hi @mayliu1,

Thank you for the reply. 

Using oscilloscope, we have verified that the reset pin (POR_B) is pulled low immediately on power-up. It remains low until after VDD_SNVS_IN, DCDC_IN, and DCDC_PSWITCH finish ramping up to 3.3 V. This seems normal as we are using the internal DC-DC.

SWD signals are stable with clean transitions between high and low logic levels. I am not certain if the data being transmitted is correct or not.

We have tried all SWD debug speed options that are available in the P&E tool. The results are the same.

We have checked that BOOT_MODE logic levels are correct. We tried both, BOOT_MODE=01 and BOOT_MODE=10 (serial downloader and internal flash boot), but results are the same.

All BOOT_CFG pins are pulled down.

Do you have any other ideas as to what else should be checked?

Regards,
Jason

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mayliu1
NXP Employee
NXP Employee

Hi @jlzm ,

Thanks for your updated information.

First, I suggest you check whether your board power on is success.

Please check the power on sequence is correct as the following Fig show.

https://www.nxp.com/webapp/Download?colCode=MIMXRT105060HDUG

mayliu1_0-1752637519263.png

Please note that DCDC_PSWITCH need be delayed more than 1 ms to switch on the internal DCDC.

Second,  did you try to set your board in serial downloader mode, and use LPUART1 or USB to connect your PC and board by using SEC Tool.

https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools...

If you can connect your bard by UART1 or USB, it means your board power on is success.

Third, did you try to use J-link device to debug by use SWD(default SWD)

mayliu1_1-1752637920727.png

Wish it helps you.
If you still have question about it, please kindly let me know.

Wish you a nice day!

Best Regards
MayLiu

 

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jlzm
Contributor II

Hi @mayliu1 ,

We have checked the power-on sequence and verified it meets the requirement defined in the RT1064 datasheet. In our design, VDD_SNVS_IN, VDD_HIGH_IN, and DCDC_IN are shorted together. DCDC_PSWITCH is delayed to >1 ms after DCDC_IN is stable. The POR_B is held low during the power-up sequence. Afterwards, we can see that DCDC_LP is outputting about +1.15V. The 24 MHz oscillator circuit is also running.

We have tried changing BOOT_MODE to boot into Serial Downloader mode. We get the same result where the debugger is unable to put the RT1064 into debug mode.

We do not have J-Link debuggers available at the moment. However, it should be noted that this P&E MultiLink unit works fine on our other custom boards that also use RT1064 microcontroller.

We have also done a thorough review of the design schematic to make sure that there are no other power supply rails driving any of the microcontroller pins prior to its being powered-on.

Any other possible things that could cause the microcontroller to do this?

Regards,

Jason

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mayliu1
NXP Employee
NXP Employee

Hi @jlzm ,

Thanks for your updated information.

The current status cannot determine whether the chip is operating normally or if there is a hardware design issue related to the SWD circuit.

So I suggest you can use SEC Tool to boot the RT1064. If the RT1064 board can connect with PC by LPUART1 or USB1, it means the RT1064 chip work well, then we can continue find root cause.

https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools...

mayliu1_1-1752740019445.png

 

1: set RT1064 board as serial downloader mode.

2:open SEC Tool, create a new workspace about RT1064

3: connect by LPUART1 or USB(depend on your bard design)

mayliu1_0-1752739954068.png

Please try it.

 

Best Regards

MayLiu

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