I saw the follwing power sequence from datasheet, is it correct ?
Any other HW concern ?
3.2.3 SRTC DryIce Power-Up/Down Sequence
In order to guarantee DryIce power-loss protection, including retention of SRTC time data during power
down, users must do the following:
• Place a proper capacitor on the NVCC_DRYICE output pin, and
• Implement the below power-up/down sequence
1. Assert power on reset (POR).
2. Turn on NVCC_CRM.
3. Turn on QVDD digital logic domain supplies for not less than 1 ms and not more than 32 ms, after
NVCC_CRM reaches 90% of 3.3 V.
NOTE
This is to guarantee that POR is stable already at NVCC_CRM/QVDD
power domain interface before QVDD is turned on, and POR instantly
propagates to QVDD domain after QVDD is turned on.
4. Turn on other NVCCx digital I/O power supplies for not less than 1 ms and not more than 32 ms,
after QVDD reaches 90% of 1.2 V.
5. Turn on all other analog power supplies, including USBPHY1_VDDA_BIAS,
USBPHY1_UPLL_VDD, USBPHY1_VDDA, USBPHY2_VDD, NVCC_ADC,
OSC24M_VDD, MPPLL_VDD, UPLL_VDD, and FUSEVDD (FUSEVDD is tied to GND if
fuses are not programmed) for not less than 1 ms and not more than 32 ms, after NVCCx reaches
90% of 3.3 V.
NOTE
This is to guarantee that analog peripherals can get properly initialized
(reset) values from QVDD domain and NVCCx domain.
6. Negate the POR signal for at least 90 μ s after all previous steps.
NOTE
• This is to guarantee that both POR logic and clocks are stable inside the
i.MX25 chip, before POR is removed.
• The dV/dT should be no faster than 0.25 V/us for all power supplies, to
avoid triggering ESD circuit.
In addition, the following power-down sequence is recommended:
1. Turn off power for analog parts, including USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD,
USBPHY1_VDDA, USBPHY2_VDD, NVCC_ADC, and FUSEVDD (FUSEVDD is tied to GND
if fuses are not programmed).
2. Turn off QVDD.
3. Turn off NVCCx, PLL, OSC, and other powers.
NOTE
The power-down steps can be executed simultaneously, or very shortly one
after another.
