linux on imx28 customized board

[pt]

Hi igorpadykov,

Processor:IMX281

Linux Kernel version:2.6.35

Linux BSP:L2.6.35_1.1.0_130130_source

I have built imx28_ivt_linux.sb for my custom board.

We are using  VDD 5V only.  Thus  I have define

     #define NO_DCDC_BATT_SOURCE(in power_prep.c)

Successfully booted up from SD.

But stuck at "uncompressing linux"

HTLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLFLC

PowerPrep start initialize power...

Configured for 5v only power source.            Battery powered operation disabled.

LLLCOct 15 201416:41:58

FRAC 0x92925552

memory type is DDR2

                   Wait for ddr ready 1power 0x00820710

Frac 0x92925552

start change cpu freq

hbus 0x00000003

cpu 0x00010001

LLLLLLLFLCLLJUncompressing Linux...

Repeats the sequence and stuck at "uncompressing Linux..."How can I solve this issue?

I have used uboot boot stream image too.

PowerPrep start initialize power...

Configured for 5v only power source.            Battery powered operation disabled.

Dec 16 201412:41:33

FRAC 0x92925552

memory type is DDR2

                   Wait for ddr ready 1power 0x00820710

Frac 0x92925552

start change cpu freq

hbus 0x00000003

cpu 0x00010001

start test memory accress

ddr2 0x40000000

finish simple test

U-Boot 2009.08 (Dec 02 2014 - 12:15:23)

Freescale i.MX28 family

CPU:   454 MHz

BUS:   151 MHz

EMI:   205 MHz

GPMI:   24 MHz

SSP0:   24 MHz

SSP2:   96 MHz

DRAM:  128 MB

PowerPrep start initialize power...

Configured for 5v only power source.            Battery powered operation disabled.

Dec 16 201412:41:33

FRAC 0x92925552

memory type is DDR2

                   Wait for ddr ready 1power 0x00820710

Frac 0x92925552

start change cpu freq

hbus 0x00000003

cpu 0x00010001

start test memory accress

ddr2 0x40000000

finish simple test

Repeating this sequence,not going beyond it.

Regards

Pt

Message was edited by: Pt A R

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[igorpadykov]

Hi Pt

these are caused by DDR errors, you should find new DDR settings from below

Board Bring-up and DDR Initialization Tools

then modify DDR2EmiController_EDE1116_200MHz(void) in init-mx28.c

bootlets.

~igor

[pt]

Hi igorpadykov

I am using ELPIDA E116AEBD DDR2 .

I have tested DDR2 using memory test code (mem_test).

It works fine.

At first it just displayed 'simsimsimsim' only.

Problem at power_prep section.

So I changed the value of HW_POWER_5VCTRL (clear the value of bit 0,  i.e., disable DCDC).

Now the DDR2 test code works well.

................................................................................................................................................

simple test

DDR test passed

t0: memcpy11 SSN test

t1: memcpy8 SSN test

t2: memcpy11 random pattern test

.....t3: byte-wise SSN test

pass

cycle pass

simple test

DDR test passed

t0: memcpy11 SSN test

t1: memcpy8 SSN test

t2: memcpy11 random pattern test

.....t3: byte-wise SSN test

.....................................................................................................................................................................................................

But I couldn't resolve that linux and uboot starting issue.

Regards

Pt

[igorpadykov]

Hi Pt

do you mean that you do not use DC-DC at all,

even with VDD4P2 ?

~igor

[pt]

Hi igorpadykov,

I am using DCDC. But the code worked when I disable that bit.

I think when  switch from linear regulator to DCDC, there is some power issue.

Is there any problem in my circuit design?

Regards

Pt

[igorpadykov]

you should find reason why ddr test does not work with DCDC (probably it is erratum 5837),

may be for that reason linux is not working too.

There are many ways to debug it, one - use OBDS (run it with jtag)

"IMX_OBDS  : On-Board Diagnostic Suit for the i.MX28"

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MCIMX28EVKJ&fpsp=1&tab=Design_Tools_T...

[pt]

Hi igorpadykov

     Thank you.

     The issue was due to brownout.

Regards

Pt

[igorpadykov]

[pt]

Hi igorpadykov

Ok.Thank you.I will study this.

But when I test the ddr using OBDS tool suite, DDR test passed.

Regards

Pt