Hi,
I'm working with the mhdp/dcss driver based off of NXPs BSP and am using the 8.7 firmware from
https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.7.bin
While 4-Lane DisplayPort configurations work, dual lane configurations fail the link training like (i've added some printk to the training code in cdns-mhdp-common.c):
[ 61.093206] cdns-mhdp-imx 32c00000.hdmi: [drm:cdns_mhdp_train_link [cdns_mhdp_drmcore]] Training status: 0x4
[ 61.148744] cdns-mhdp-imx 32c00000.hdmi: [drm:cdns_mhdp_train_link [cdns_mhdp_drmcore]] Training status: 0x20
...
[ 61.541297] cdns-mhdp-imx 32c00000.hdmi: [drm:cdns_mhdp_train_link [cdns_mhdp_drmcore]] Training status: 0x0
[ 61.551221] cdns-mhdp-imx 32c00000.hdmi: [drm:cdns_mhdp_train_link [cdns_mhdp_drmcore]] *ERROR* training failed: -110
[ 61.561890] cdns-mhdp-imx 32c00000.hdmi: [drm:cdns_mhdp_train_link [cdns_mhdp_drmcore]] *ERROR* Failed to start training -110
[ 61.573294] cdns-mhdp-imx 32c00000.hdmi: [drm:cdns_dp_mode_set [cdns_mhdp_drmcore]] *ERROR* Failed link train -110
So the training can finish clock recovery but gives up with
EQ_PHASE_FAILED
Are there any special settings required to switch to 2 lane mode. Can someone confirm this should work ?
The reference manual does not give any details on how to configure two lane mode. I can see that the number of lanes is passed down to the phy and used in
cdns_mhdp_set_host_cap()
I assume it should not affect the LANES_CONFIG register, right?
Can you please specify the details of correct PHY and HDMITX setup for two lane DP mode on the imx8mq?