HI @Navee_nK!
Based on the i.MX 8M Plus Reference Manual, the values for csis-hs-settle and csis-clk-settle in the device tree are determined by the MIPI D-PHY timing requirements, which are directly influenced by the CSI interface data rate.
These parameters are configured through the following registers:
HSSETTLE[7:0] → corresponds to csis-hs-settle
CLKSETTLECTL[1:0] → corresponds to csis-clk-settle
To ensure proper bandwidth matching between the CSI receiver and the image sensor, the following equation must be satisfied:
RX_BYTE_CLK_HS×Number of Data Lanes×8≤Pixel Clock×Bitwidth of Image Format×Pixels per Clock
This formula and its context are documented in the MIPI CSI Host Controller section of the Reference Manual, specifically on page 5364.
Best Regards,
Chavira