Hello,
I am working on imx8mp PhyTec SoM module and connected a LVDS to MIPI bridge on CSI0 with a 2-lane configuration. The bridge is generating a test pattern and I am trying to understand on how to configure the clocks for this configuration.
I am able to capture the image from the camera, but it is not coming out to be right.
Below is the DTS configuration that I have been trying.
The commented lines, is everything I have tried so far.
The I2C of the bridge is working properly and I get debug output from it.
The bridge is using a pixel clock frequency of 74.25 MHz. It has been configured with 1920x1080 at 60Hz signal.
Total Pixels Per Second=1920×1080×60=124,416,000
Data Rate=74.25×106×24 bits =1.782 Gbps (total). For two lanes it will be 891 Mbps.
And since DDR operates at twice rate, the clock frequency for MIPI will be 445.5 MHz.
Hence I tried configuring link-frequencies / clock-frequency to multiple of such values. However I don't get the right image.
In the kernel logs, I see the error:
[ 472.546870] mxc-mipi-csi2.0: Frame End events: 3
[ 472.551485] mxc-mipi-csi2.0: Frame Start events: 235
[ 472.556446] mxc-mipi-csi2.0: Non-image data after odd frame events: 0
[ 472.562882] mxc-mipi-csi2.0: Non-image data before odd frame events: 0
[ 472.569406] mxc-mipi-csi2.0: Non-image data after even frame events: 0
[ 472.575930] mxc-mipi-csi2.0: Non-image data before even frame events: 0
[ 472.582540] mxc-mipi-csi2.0: Unknown Error events: 1277
[ 472.587762] mxc-mipi-csi2.0: CRC Error events: 87
[ 472.592464] mxc-mipi-csi2.0: ECC Error events: 43758
[ 472.597425] mxc-mipi-csi2.0: FIFO Overflow Error events: 0
[ 472.602907] mxc-mipi-csi2.0: Lost Frame End Error events: 231
[ 472.608651] mxc-mipi-csi2.0: Lost Frame Start Error events: 3
[ 472.614393] mxc-mipi-csi2.0: SOT Error events: 40031
My question is:
1. Am I missing anything in clock configuration?
2. Is there anything in ISI block, that I need to configuration?
3. Should there be anything else I should be concerned about? Any other parameters?
DTS configuration:
&cameradev {
status = "okay";
cap_device {
status = "okay";
};
};
&i2c3 {
status = "okay";
lvds_bridge {
reg = <0x5A>;
status = "okay";
compatible = "lt9211c";
#address-cells = <0x1>;
#size-cells = <0x0>;
//mclk = <24000000>;
//mclk_source = <0>;
//mipi-csi;
port {
lt9211c_ep: endpoint {
data-lanes = <1 2>;
clock-lanes = <0>;
bus-type = <4>;
clock-noncontinuous = <1>;
//link-frequencies = /bits/ 64 <450000000>;
remote-endpoint = <&mipi_csi0_ep>;
clock-frequency = <74250000>; // Pixel clock in Hz (74.25 MHz)
hsync-active = <0>; // Sync polarity
vsync-active = <0>;
pclk-sample = <1>; // Sample on rising edge
};
};
};
};
&isi_0 {
status = "okay";
cap_device {
status = "okay";
};
m2m_device {
status = "disabled";
};
};
&isi_1 {
status = "disabled";
cap_device {
status = "okay";
};
};
&mipi_csi_0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
//assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
//assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
//assigned-clock-rates = <500000000>;
// clock-frequency = <500000000>;
clock-frequency = <74250000>; // 74.25 MHz
//max-pixel-frequency = /bits/ 64 <266000000>;
//link-frequencies = /bits/ 64 <505500000>;
//max-lane-frequency = /bits/ 64 <750000000>;
//max-data-rate = /bits/ 64 <0>;
//link-frequencies = /bits/ 64 <750000000>;
//max-lane-frequency = /bits/ 64 <750000000>;
//max-pixel-frequency = /bits/ 64 <266000000>;
//max-data-rate = /bits/ 64 <0>;
//link-frequencies = /bits/ 64 <505500000>;
//clock-frequency = <505500000>;
//link-frequencies = /bits/ 64 <1011000000>;
//clock-frequency = <1011000000>;
port@0 {
reg = <0>;
mipi_csi0_ep: endpoint {
remote-endpoint = <<9211c_ep>;
data-lanes = <2>;
csis-hs-settle = <4>;
csis-clk-settle = <2>;
csis-wclk;
bus-type = <4>; /* 4 = MIPI CSI-2 D-PHY */
//mclk = <24000000>;
//mclk_source = <0>;
//mclk = <74_250000>; // Pixel clock in Hz (74250 kHz)
//link-frequencies = /bits/ 64 <505500000>; // Mentioned in the LT9211 datasheet
//max-pixelrate = <74250000>; // Mentioned in the LT9211 datasheet
};
};
};
&mipi_csi_1 {
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <1>;
mipi_csi1_ep: endpoint {};
};
};
Captured image:
