imx8mp 8GByte LPDDR4 definition

[AngelF]

Hello,

We have our own design based on imx8mp. Up to now we have been using 4GByte LPDDR4 and now we want to change to 8GByte LPDDR4 memory.

We use NXP excel to generate .ds file. Then with this .ds file and NXP DDR tool we generate lpddr4_timing.c file for u-boot.

Excel config parameters for 4GByte memory are

Density per channel per chip select (Gb)1:	8
Number of Channels	2
Number of Chip Selects used2	2
Total DRAM density (Gb)	32
Number of ROW Addresses2	16
Number of COLUMN Addresses2	10
Number of BANK addresses2	3
Number of BANKS2	8
Bus Width	32
Clock Cycle Freq (MHz)3	1500
Clock Cycle Time (ns)	0,666666666666667
FREQ1 setpoint Clock Cycle Freq (MHz)	200
FREQ1 Clock Cycle Time (ns)	5
FREQ2 setpoint Clock Cycle Freq (MHz)	50
FREQ2 Clock Cycle Time (ns)	20

What do we need to change for this new 8GByte memory (2 channels ×16 I/O × 2 ranks) ?

Best regards and thank you

Angel

[Chavira]

Hi @AngelF,

Thank you for contacting NXP Support!

After updating the device tree and timing file, you’ll also need to update the RAM size in your board’s U-Boot configuration file.

imx8mp_evk.h (Example) 

If you're using OP-TEE, make sure to update the RAM size in the corresponding configuration file as well.

conf.mk 

Best regards,
Chavira

[AngelF]

Hello Chavira.
Thank you for your help.
But first, to generate timing file, what values do we need to change for this memory in the table a sent before ?
Best regards and thank you
Angel

[Chavira]

Hi @AngelF,

You should adjust those parameters based on the specific part number of the memory you're using.

The required specifications can be found in the datasheet for that memory component. Make sure to refer to it to ensure correct configuration.

Best regards,
Chavira

[AngelF]

Hello Chavira,
Yes, you are right, but I can not find the correct configuration.
Memory is MT53E2G32D4DE-046 AIT:C (2 Gig × 32 (2 channels ×16 I/O × 2 ranks))
In the above table only possibility is to change "Density per channel per chip select (Gb)1:" from 8 to 16 to get "Total DRAM density (Gb)" 64, but it is not working.
Definitions and devive tree are:
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G)

memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0xc0000000>,
<0x1 0x00000000 1 0x40000000>;
};
Could you please help us to get the right configuration ?
Best regards and thank you
Angel

[Chavira]

Hi @AngelF,

The following values are used to configure 8GB of RAM:

#define PHYS_SDRAM_2_SIZE 0x140000000

memory@40000000 {
    device_type = "memory";
    reg = <0x0 0x40000000 0 0xc0000000>,
          <0x1 0x00000000 0 0x140000000>;
};

The i.MX8MP platform supports two memory regions:

The first region starts at 0x40000000 and has a size of 3GB.
The second region starts at 0x100000000 and covers the remaining 5GB.

Best regards,
Chavira

[AngelF]

Hello Chavira,
Thank you for your answer.
Yes, you are right, but I am asking about values to set in file MX8M_LPDDR4_RPA_v33.xlsx from NXP. With these values we generate the initialization script to load with NXP DDR tool.
We need it to generate lpddr4_timing.c file.
Values we sent in our first post are for 4GByte memory and we need new values for the 8GByte memory MT53E2G32D4DE-046 AIT:C (2 Gig × 32 (2 channels ×16 I/O × 2 ranks))

Best regards and thank you
Angel

[Chavira]

Hi @AngelF,

According to the datasheet the correct parameters should be the next:

Parameter	Value
Density per channel per chip select (Gb)	16
Number of Channels	2
Number of Chip Selects used	2
Total DRAM density (Gb)	64
Number of ROW Addresses	16
Number of COLUMN Addresses	10
Number of BANK addresses	3
Number of BANKS	8
Bus Width	32
Clock Cycle Freq (MHz)	2133
Clock Cycle Time (ns)	0.468823
FREQ1 setpoint Clock Cycle Freq (MHz)	200
FREQ1 Clock Cycle Time (ns)	5
FREQ2 setpoint Clock Cycle Freq (MHz)	50
FREQ2 Clock Cycle Time (ns)	20

[AngelF]

Hello Chavira,
Thank you for your help.
Just one thing to point. For this memory to work also "Number of ROW Addresses" must be set from 16 to 17.
The problem is that MX8M_LPDDR4_RPA_v33.xlsx from NXP download site does not allow to set this field to 17. Only values from 13 to 16 are allowed.
I had to use an older version of this tool that allows to set 17 in this field.
Best regards and thank you
Angel

[Chavira · Accepted solution]

Hi @AngelF,

Try downloading the Config Tools for i.MX Applications Processors, in that tool we have an updated DDR Tool to generate the proper files easily.

Best Regards,
Chavira