imx8mm unable to detect a Watchdog Reset

[Jarvis3345]

Hi Team,
Im trying to enable and test the WDT on my imx8mm, Iam able to trigger the WDT within the timeout i have set by writing it to the WT bit (of WCR) and enabling the WDE bit of the WCR(watchdog control register) as per the manual.
But after every rest the WDOGx_WRSR register's POR bit and the TOUT bit is always shoing the reset as an POR.
As per the description it is clear that the WRSR is not cleared by a hard reset
Any help on the above issue will be helpful.

[Jarvis3345 · Accepted solution]

I have found the issue the watchdog reset is resulting  both cold boot and WD reset because of which the  SOC’s SRSR register is reporting the same cause which is PO reset
solution is by reading the i2c register value of the PMIC using i2cget -f -y 0 0x4b 0x29 since my PMIC is bd71847
Thanks

[Bio_TICFSL]

Hello,

Which is your routine to clear and to enable the watchdog?, since you can do it with the BSP.

Regards

[Jarvis3345]

I'm integrating my code onto the uboot source code and enabling the WDT.
since a 16 bit acces is required im making use of this method

#define writew(val, addr) (void)((*(volatile uint16_t *)(addr)) = (val))
//service the wdt
writew(0x5555, 0x30280002)

writew(0xAAAA, 0x30280002)
//enable wde bit of WCR

wde = *(volatile uint16_t *)(0x30280000 );

wde |= 0x0004;

writew(wde, 0x30280000);

Let me know if there is any other way possible to achieve the same a detect a WDT reset.