imx8mm (mini), how to calculate value for hs-settle ?

[bhgu]

I see the table for hs-settle for imx8mm through the link as below

https://community.nxp.com/t5/i-MX-Processors/Explenation-for-HS-SETTLE-parameter-in-MIPI-CSI-D-PHY-r...

but I want to know  [ the value as time ]

because now I struggled timing issue for MIPI-CSI between FPGA and imx8mm

I got the SOT error from MIPI-CSI interrupt handler as below

[ 342.595878] <mipi_csis_irq_handler> SOT Error: 1
[ 342.600507] <mipi_csis_irq_handler> CRC Error: 16
[ 342.605208] <mipi_csis_irq_handler> Frame Start: 15
[ 342.610082] <mipi_csis_irq_handler> Frame End: 14
[ 342.616155] <mipi_csis_irq_handler> CRC Error: 17

to sum up,

1. how to calculate value as time for hs-settle? or what is value as time for hs-settle 26 on table?

2. If I can't know the value as time, Is it okay(spec in) if mipi-csi TX IP set the hs-settle 312ns( tHS-prepare value 50ns, tHS-zero 262ns?

Thank you for your help in advance

[Zhiming_Liu]

Hi @bhgu 

1. how to calculate value as time for hs-settle? or what is value as time for hs-settle 26 on table?

-->The timing in i.MX8MM is calculated by Samaung timing tool 

[bhgu]

thank you for your reply

i saw that table at link below

https://community.nxp.com/t5/i-MX-Processors/Explenation-for-HS-SETTLE-parameter-in-MIPI-CSI-D-PHY-r...

but one of your employee said "

The above table 34 and Table 35 are for iMX8MQ, not for iMX8MM. The iMX8MM MIPI CSI2 should reference to iMX7D's. Table for HSSETTLE[7:0] and CLKSETTLECTL[1:0]."

which one is correct?

[Zhiming_Liu · Accepted solution]

According to the MIPI CSI2 D-PHY specification shown below, the minimum Ths_settle = 85ns + 6UI and the maximum Ths_settle = 145ns + 10UI, where UI is the period the HS data rate on the MIPI CSI data lanes, since the high speed (HS) data is transmitted in DDR (rising edge and falling edge of the clock) mode, 1 UI = 1/2 period of the MIPI CSI HS clock.

In calculation of the Ths_setttle, the HSSTTEL bit field is combined with the period of the LP clock whose maximum frequency is 10MHz, its period (Tlp) is 100ns then. That is Ths_settle = Tlp + Tlp / HSSETTL[7:0] = 100ns + 100ns / HSSETTL[7:0].

The "MIPI Serial clock Frequency (MHz)" in the Excel table shall be modified as "MIPI Serial data rate (Mbps)". That is the MIPI CSI HS clock frequency is half of the MIPI serial data rate. The minimum data rate of the MIPI CSI D-PHY is 80Mbps and the maximum data rate is 1500Mbps.

You shall set the HSSETTLE[7:0] bit field according to the actual MIPI CSI HS clock frequency setting.

If the MIPI CSI HS clock frequency is  150MHz, that means the data rate is 300Mbps and it shall be set as HSSETTLE[7:0] = 6 for Ths_settle = 100ns + 100ns / 6 = 117ns. It meets the requirement of [85ns + 6UI = 85ns + 6 x 1000ns / 300 = 105ns] < Ths_settle < [45ns + 10UI = 145ns + 10 x 1000ns / 300 = 178ns].

[bhgu]

thank you for the kind explanation. It helped me alot

my date rate is 1200Mbps so HS-SETTLE is 103.85ns (table value is 26, Ths-settle is 100+100/26). 

can I understand correctly?

(and also the value meet condition that minimum is 90 (85+6*1000/1200) and maximum is 153.3 (145+10*1000/1200)).

pixel clock is not related to hs-settle ?

period of the LP clock whose maximum frequency is 10MHz is fixed value when to calculate?

thanks