Hi,
I am trying to config imx8m nano ethernet interface into RMII mode. However I have met problem on ETH REF CLK.
I am using an external 50MHz crystal to feed clock into imx8m nano as eth ref clk.
My dts file looks as below:
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1_b>;
phy-mode = "rmii";
//phy-handle = <ðphy0>;
fsl,magic-packet;
phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
//phy-reset-duration = <25>;
//phy-reset-post-delay = <100>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
<&clk IMX8MN_SYS_PLL2_100M>,
<&clk IMX8MN_SYS_PLL2_50M>,
<&clk IMX8MN_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <50000000>, <0>;
status = "okay";
fixed-link {
speed = <100>;
full-duplex;
};
/*mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
max-speed = <100>;
};
};*/
};
&iomuxc {
pinctrl_fec1_b: fec1-bgrp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x03
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56
MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 /* MODE0 */
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 /* MODE1 */
MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x110 /* PHYAD2 */
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 /* CLK125_EN */
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 /* LED_MODE */
>;
};
};
By this configuration I am expecting ENET_TD2 pad is muxed to be ref clk input.
I try to verify the pin config after boot the system up by reading pad registers value using mem tool. All looks right but the IOMUXC_GPR_GPR1 register content.
According to the chip reference manual, the GPR_ENET1_ TX_CLK_SEL bit of this register is '0' by default, but now it reads "0x00002000", which means the ENET_TD2 pad been set to output of ref clk instead of input as I desired.
I did not change any other source code. So I am not sure why IOMUXC_GPR_GPR1 value is not as expected. Is there any other thing may change the value of this reg?
Please hint me if I missed something.
thank you very much.
/Roland
