imx8m mini custom board uboot issue

Dhevan · ‎03-11-2021

Hi,

BSP Version - 5.4.24

Imx8m mini evk board uboot device tree customized bused on our custom hardware.

I have removed all the audio related codes.

Even though uboot printing some warning messages.

Found /vpu_g1@38300000 node
Modify /vpu_g1@38300000:status disabled
Found /vpu_g2@38310000 node
Modify /vpu_g2@38310000:status disabled
Found /vpu_h1@38320000 node
Modify /vpu_h1@38320000:status disabled
Found /cpus/cpu@2 node
Delete node /cpus/cpu@2
Found /cpus/cpu@3 node
Delete node /cpus/cpu@3

Why this error log is printing ?

How to solve this issue ?

Thanks & Regards,

Vasu

Zhiming_Liu · ‎03-11-2021

Hi

Can you provide the dts andt all the files you changed?

The error shows the dts has errors

BR

Zhiming

Dhevan · ‎03-11-2021

Hi @Zhiming_Liu ,

Please look into attached dts files.

imx8mm-evk.dts :

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

/dts-v1/;

#include <dt-bindings/usb/pd.h>
#include "imx8mm.dtsi"

/ {
	model = "NXP i.MX8MM EVK board";
	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";

	chosen {
		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
		stdout-path = &uart2;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_led>;

		status {
			label = "status";
                        gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		pt_opt1{
			label = "pt_opt1";
			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		pt_opt2 {
			label = "pt_opt2";
                        gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	reg_usdhc1_vmmc: regulator-usdhc1 {
		compatible = "regulator-fixed";
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	flash0: mt25qu256aba@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <80000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;

	pmic: pca9450@25 {
                compatible = "nxp,pca9450";
                reg = <0x25>;
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio1>;
		interrupts =  GPIO_ACTIVE_LOW>;

   		   regulators {
			pca9450,pmic-buck2-uses-i2c-dvs;
			/* Run/Standby voltage */
			pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;

			buck1_reg: regulator@0 {
				reg = <0>;
				regulator-compatible = "buck1";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck2_reg: regulator@1 {
				reg = <1>;
				regulator-compatible = "buck2";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
				nxp,dvs-run-voltage = <1000000>;
				nxp,dvs-standby-voltage = <900000>;
			};

			buck4_reg: regulator@3 {
				reg = <3>;
				regulator-compatible = "buck4";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5_reg: regulator@4 {
				reg = <4>;
				regulator-compatible = "buck5";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6_reg: regulator@5 {
				reg = <5>;
				regulator-compatible = "buck6";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1_reg: regulator@6 {
				reg = <6>;
				regulator-compatible = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2_reg: regulator@7 {
				reg = <7>;
				regulator-compatible = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1150000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3_reg: regulator@8 {
				reg = <8>;
				regulator-compatible = "ldo3";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4_reg: regulator@9 {
				reg = <9>;
				regulator-compatible = "ldo4";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo5_reg: regulator@10 {
				reg = <10>;
				regulator-compatible = "ldo5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
               };
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
	cd-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc1_vmmc>;
	status = "okay";
};

&snvs_pwrkey {
	status = "okay";
};

&uart2 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usbotg1 {
	status = "okay";
};

&usbotg2 {
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";

	pinctrl_flexspi0: flexspi0grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
		>;
	};

	pinctrl_gpio_led: gpioledgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5      	       0x19
                        MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6              0x19
                        MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16           0x19
		>;
	};

	pinctrl_gpio_wlf: gpiowlfgrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
		>;
	};

	pinctrl_i2c1_gpio: i2c1grp-gpio {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14        		0x1c3
			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15        	0x1c3
		>;
	};

	pinctrl_i2c2_gpio: i2c2grp-gpio {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16        		0x1c3
			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17        	0x1c3
		>;
	};

	pinctrl_i2c3_gpio: i2c3grp-gpio {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18        		0x1c3
			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19        	0x1c3
		>;
	};

	pinctrl_pmic: pmicirq {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc1_gpio: usdhc1grpgpio {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x41
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
		>;
	};

};

imx8mm-evk-u-boot.dtsi :

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019 NXP
 */

/ {

	aliases {
		usbgadget0 = &usbg1;
		usbgadget1 = &usbg2;
	};

	usbg1: usbg1 {
		compatible = "fsl,imx27-usb-gadget";
		dr_mode = "peripheral";
		chipidea,usb = <&usbotg1>;
		status = "okay";
	};

	usbg2: usbg2 {
		compatible = "fsl,imx27-usb-gadget";
		dr_mode = "peripheral";
		chipidea,usb = <&usbotg2>;
		status = "okay";
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};

&{/soc@0} {
	u-boot,dm-pre-reloc;
	u-boot,dm-spl;
};

&clk {
	u-boot,dm-spl;
	u-boot,dm-pre-reloc;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-parents;
	/delete-property/ assigned-clock-rates;
};

&osc_24m {
	u-boot,dm-spl;
	u-boot,dm-pre-reloc;
};

&aips1 {
	u-boot,dm-spl;
	u-boot,dm-pre-reloc;
};

&aips2 {
	u-boot,dm-spl;
};

&aips3 {
	u-boot,dm-spl;
};

&iomuxc {
	u-boot,dm-spl;
};

&reg_usdhc1_vmmc {
	u-boot,dm-spl;
};

&pinctrl_uart2 {
	u-boot,dm-spl;
};

&pinctrl_usdhc1_gpio {
	u-boot,dm-spl;
};

&pinctrl_usdhc1 {
	u-boot,dm-spl;
};

&pinctrl_usdhc3 {
	u-boot,dm-spl;
};

&gpio1 {
	u-boot,dm-spl;
};

&gpio2 {
	u-boot,dm-spl;
};

&gpio3 {
	u-boot,dm-spl;
};

&gpio4 {
	u-boot,dm-spl;
};

&gpio5 {
	u-boot,dm-spl;
};

&uart2 {
	u-boot,dm-spl;
};

&usdhc1 {
	u-boot,dm-spl;
	sd-uhs-sdr104;
	sd-uhs-ddr50;
	assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
	assigned-clock-rates = <400000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
};

&usdhc3 {
	u-boot,dm-spl;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
	assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
	assigned-clock-rates = <400000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
};

&i2c1 {
	u-boot,dm-spl;
};

&pinctrl_i2c1 {
	u-boot,dm-spl;
};

&pinctrl_pmic {
	u-boot,dm-spl;
};

&flexspi {
	assigned-clock-rates = <100000000>;
	assigned-clocks = <&clk IMX8MM_CLK_QSPI>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
};

imx8mm.dtsi :

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

#include <dt-bindings/clock/imx8mm-clock.h>
#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/imx8mm-dispmix.h>
#include <dt-bindings/thermal/thermal.h>

#include "imx8mm-pinfunc.h"

/ {
	compatible = "fsl,imx8mm";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec1;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		spi0 = &flexspi;
		usb0 = &usbotg1;
		usb1 = &usbotg2;
		video0 = &lcdif;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		idle-states {
			entry-method = "psci";

			cpu_pd_wait: cpu-pd-wait {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010033>;
				local-timer-stop;
				entry-latency-us = <1000>;
				exit-latency-us = <700>;
				min-residency-us = <2700>;
			};
		};

		A53_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clk IMX8MM_CLK_ARM>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			nvmem-cells = <&cpu_speed_grade>;
			nvmem-cell-names = "speed_grade";
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clk IMX8MM_CLK_ARM>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clk IMX8MM_CLK_ARM>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clk IMX8MM_CLK_ARM>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_L2: l2-cache0 {
			compatible = "cache";
		};
	};

	a53_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <850000>;
			opp-supported-hw = <0xe>, <0x7>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};

		opp-1600000000 {
			opp-hz = /bits/ 64 <1600000000>;
			opp-microvolt = <900000>;
			opp-supported-hw = <0xc>, <0x7>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};

		opp-1800000000 {
			opp-hz = /bits/ 64 <1800000000>;
			opp-microvolt = <1000000>;
			opp-supported-hw = <0x8>, <0x3>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	osc_32k: clock-osc-32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "osc_32k";
	};

	osc_24m: clock-osc-24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc_24m";
	};

	clk_ext1: clock-ext1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext1";
	};

	clk_ext2: clock-ext2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext2";
	};

	clk_ext3: clock-ext3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext3";
	};

	clk_ext4: clock-ext4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency= <133000000>;
		clock-output-names = "clk_ext4";
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7
			     (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
		interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
	};

	power-domains {
		compatible = "simple-bus";
		/* HSIO SS */
		hsiomix_pd: hsiomix-pd {
			compatible = "fsl,imx8m-pm-domain";
			#power-domain-cells = <0>;
			domain-index = <0>;
			domain-name = "hsiomix";
			clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
		};

		usb_otg1_pd: usbotg1-pd {
			compatible = "fsl,imx8m-pm-domain";
			#power-domain-cells = <0>;
			domain-index = <2>;
			domain-name = "usb_otg1";
			parent-domains = <&hsiomix_pd>;
		};

		usb_otg2_pd: usbotg2-pd {
			compatible = "fsl,imx8m-pm-domain";
			#power-domain-cells = <0>;
			domain-index = <3>;
			domain-name = "usb_otg2";
			parent-domains = <&hsiomix_pd>;
		};

		/* GPU SS */
		gpumix_pd: gpumix-pd {
			compatible = "fsl,imx8m-pm-domain";
			#power-domain-cells = <0>;
			domain-index = <4>;
			domain-name = "gpumix";
			clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
				 <&clk IMX8MM_CLK_GPU_AHB>,
				 <&clk IMX8MM_CLK_GPU2D_ROOT>,
				 <&clk IMX8MM_CLK_GPU3D_ROOT>;
		};

		/* DISP SS */
		dispmix_pd: dispmix-pd {
			compatible = "fsl,imx8m-pm-domain";
			#power-domain-cells = <0>;
			domain-index = <9>;
			domain-name = "dispmix";
			clocks = <&clk IMX8MM_CLK_DISP_ROOT>,
				 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
				 <&clk IMX8MM_CLK_DISP_APB_ROOT>;
		};

		mipi_pd: mipi-pd {
			compatible = "fsl,imx8m-pm-domain";
			#power-domain-cells = <0>;
			domain-index = <10>;
			domain-name = "mipi";
			parent-domains = <&dispmix_pd>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
		clock-frequency = <8000000>;
		arm,no-tick-in-suspend;
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tmu>;
			trips {
				cpu_alert0: trip0 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit0: trip1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	usbphynop1: usbphynop1 {
		compatible = "usb-nop-xceiv";
		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
		clock-names = "main_clk";
	};

	usbphynop2: usbphynop2 {
		compatible = "usb-nop-xceiv";
		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
		clock-names = "main_clk";
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x3e000000>;

		caam_sm: caam-sm@100000 {
			compatible = "fsl,imx6q-caam-sm";
			reg = <0x100000 0x8000>;
		};

		aips1: bus@30000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x30000000 0x30000000 0x400000>;

			sai1: sai@30010000 {
				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
				reg = <0x30010000 0x10000>;
				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
					 <&clk IMX8MM_CLK_SAI1_ROOT>,
					 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
				dma-names = "rx", "tx";
				fsl,dataline = <0 0xff 0xff>;
				status = "disabled";
			};

			sai2: sai@30020000 {
				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
				reg = <0x30020000 0x10000>;
				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
					<&clk IMX8MM_CLK_SAI2_ROOT>,
					<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			sai3: sai@30030000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
				reg = <0x30030000 0x10000>;
				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
					 <&clk IMX8MM_CLK_SAI3_ROOT>,
					 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			sai5: sai@30050000 {
				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
				reg = <0x30050000 0x10000>;
				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
					 <&clk IMX8MM_CLK_SAI5_ROOT>,
					 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
				dma-names = "rx", "tx";
				fsl,dataline = <0 0xf 0xf>;
				status = "disabled";
			};

			sai6: sai@30060000 {
				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
				reg = <0x30060000 0x10000>;
				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
					 <&clk IMX8MM_CLK_SAI6_ROOT>,
					 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			gpio1: gpio@30200000 {
				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
				reg = <0x30200000 0x10000>;
				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 10 30>;
			};

			gpio2: gpio@30210000 {
				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
				reg = <0x30210000 0x10000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 40 21>;
			};

			gpio3: gpio@30220000 {
				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
				reg = <0x30220000 0x10000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 61 26>;
			};

			gpio4: gpio@30230000 {
				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
				reg = <0x30230000 0x10000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 87 32>;
			};

			gpio5: gpio@30240000 {
				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
				reg = <0x30240000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 119 30>;
			};

			tmu: tmu@30260000 {
				compatible = "fsl,imx8mm-tmu";
				reg = <0x30260000 0x10000>;
				clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
				#thermal-sensor-cells = <0>;
			};

			wdog1: watchdog@30280000 {
				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
				reg = <0x30280000 0x10000>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
				status = "disabled";
			};

			wdog2: watchdog@30290000 {
				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
				reg = <0x30290000 0x10000>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
				status = "disabled";
			};

			wdog3: watchdog@302a0000 {
				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
				reg = <0x302a0000 0x10000>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
				status = "disabled";
			};

			sdma2: dma-controller@302c0000 {
				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
				reg = <0x302c0000 0x10000>;
				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
					 <&clk IMX8MM_CLK_SDMA2_ROOT>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			sdma3: dma-controller@302b0000 {
				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
				reg = <0x302b0000 0x10000>;
				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
				 <&clk IMX8MM_CLK_SDMA3_ROOT>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			iomuxc: pinctrl@30330000 {
				compatible = "fsl,imx8mm-iomuxc";
				reg = <0x30330000 0x10000>;
			};

			gpr: iomuxc-gpr@30340000 {
				compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
				reg = <0x30340000 0x10000>;
			};

			ocotp: ocotp-ctrl@30350000 {
				compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon";
				reg = <0x30350000 0x10000>;
				clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
				/* For nvmem subnodes */
				#address-cells = <1>;
				#size-cells = <1>;

				cpu_speed_grade: speed-grade@10 {
					reg = <0x10 4>;
				};

				fec_mac_address: mac-address@640 {
					reg = <0x90 6>;
				};
			};

			anatop: anatop@30360000 {
				compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
				reg = <0x30360000 0x10000>;
			};

			irq_sec_vio: caam_secvio {
				compatible = "fsl,imx6q-caam-secvio";
				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				jtag-tamper = "disabled";
				watchdog-tamper = "enabled";
				internal-boot-tamper = "enabled";
				external-pin-tamper = "disabled";
			};

			caam_snvs: caam-snvs@30370000 {
				compatible = "fsl,imx6q-caam-snvs";
				reg = <0x30370000 0x10000>;
			};

			snvs: snvs@30370000 {
				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
				reg = <0x30370000 0x10000>;

				snvs_rtc: snvs-rtc-lp {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap = <&snvs>;
					offset = <0x34>;
					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
					clock-names = "snvs-rtc";
				};

				snvs_pwrkey: snvs-powerkey {
					compatible = "fsl,sec-v4.0-pwrkey";
					regmap = <&snvs>;
					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
					clock-names = "snvs";
					linux,keycode = <KEY_POWER>;
					wakeup-source;
					status = "disabled";
				};
			};

			clk: clock-controller@30380000 {
				compatible = "fsl,imx8mm-ccm";
				reg = <0x30380000 0x10000>;
				#clock-cells = <1>;
				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
					 <&clk_ext3>, <&clk_ext4>;
				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
					      "clk_ext3", "clk_ext4";
				assigned-clocks = <&clk IMX8MM_CLK_NOC>,
						<&clk IMX8MM_CLK_AUDIO_AHB>,
						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
						<&clk IMX8MM_SYS_PLL3>,
						<&clk IMX8MM_VIDEO_PLL1>;
				assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
							 <&clk IMX8MM_SYS_PLL1_800M>;
				assigned-clock-rates = <0>,
							<400000000>,
							<400000000>,
							<750000000>,
							<594000000>;
			};

			src: reset-controller@30390000 {
				compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
				reg = <0x30390000 0x10000>;
				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};
		};

		aips2: bus@30400000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x30400000 0x30400000 0x400000>;

			pwm1: pwm@30660000 {
				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
				reg = <0x30660000 0x10000>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
					<&clk IMX8MM_CLK_PWM1_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
				status = "disabled";
			};

			pwm2: pwm@30670000 {
				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
				reg = <0x30670000 0x10000>;
				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
					 <&clk IMX8MM_CLK_PWM2_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
				status = "disabled";
			};

			pwm3: pwm@30680000 {
				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
				reg = <0x30680000 0x10000>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
					 <&clk IMX8MM_CLK_PWM3_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
				status = "disabled";
			};

			pwm4: pwm@30690000 {
				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
				reg = <0x30690000 0x10000>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
					 <&clk IMX8MM_CLK_PWM4_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
				status = "disabled";
			};

			system_counter: timer@306a0000 {
				compatible = "nxp,sysctr-timer";
				reg = <0x306a0000 0x20000>;
				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&osc_24m>;
				clock-names = "per";
			};
		};

		aips3: bus@30800000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x30800000 0x30800000 0x400000>,
				 <0x8000000 0x8000000 0x10000000>;

			flexspi: spi@30bb0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mm-flexspi";
				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
				reg-names = "FlexSPI", "FlexSPI-memory";
				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
					 <&clk IMX8MM_CLK_QSPI_ROOT>;
				clock-names = "fspi", "fspi_en";
				status = "disabled";
			};

			ecspi1: spi@30820000 {
				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30820000 0x10000>;
				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
					 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			ecspi2: spi@30830000 {
				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30830000 0x10000>;
				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
					 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			ecspi3: spi@30840000 {
				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30840000 0x10000>;
				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
					 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart1: serial@30860000 {
				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
				reg = <0x30860000 0x10000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
					 <&clk IMX8MM_CLK_UART1_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart3: serial@30880000 {
				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
				reg = <0x30880000 0x10000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
					 <&clk IMX8MM_CLK_UART3_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart2: serial@30890000 {
				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
				reg = <0x30890000 0x10000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
					 <&clk IMX8MM_CLK_UART2_ROOT>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			crypto: crypto@30900000 {
				compatible = "fsl,sec-v4.0";
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				reg = <0x30900000 0x40000>;
				ranges = <0 0x30900000 0x40000>;
				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_AHB>,
					 <&clk IMX8MM_CLK_IPG_ROOT>;
				clock-names = "aclk", "ipg";

				sec_jr0: jr@1000 {
					 compatible = "fsl,sec-v4.0-job-ring";
					 reg = <0x1000 0x1000>;
					 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr1: jr@2000 {
					 compatible = "fsl,sec-v4.0-job-ring";
					 reg = <0x2000 0x1000>;
					 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr2: jr@3000 {
					 compatible = "fsl,sec-v4.0-job-ring";
					 reg = <0x3000 0x1000>;
					 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			i2c1: i2c@30a20000 {
				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a20000 0x10000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
				status = "disabled";
			};

			i2c2: i2c@30a30000 {
				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a30000 0x10000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
				status = "disabled";
			};

			i2c3: i2c@30a40000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
				reg = <0x30a40000 0x10000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
				status = "disabled";
			};

			i2c4: i2c@30a50000 {
				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a50000 0x10000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
				status = "disabled";
			};

			uart4: serial@30a60000 {
				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
				reg = <0x30a60000 0x10000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
					 <&clk IMX8MM_CLK_UART4_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			mu: mu@30aa0000 {
				compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
				reg = <0x30aa0000 0x10000>;
				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_MU_ROOT>;
				clock-names = "mu";
				#mbox-cells = <2>;
			};

			usdhc1: mmc@30b40000 {
				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b40000 0x10000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MM_CLK_USDHC1_ROOT>;
				clock-names = "ipg", "ahb", "per";
				assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
				assigned-clock-rates = <400000000>;
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: mmc@30b50000 {
				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b50000 0x10000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MM_CLK_USDHC2_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc3: mmc@30b60000 {
				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b60000 0x10000>;
				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MM_CLK_USDHC3_ROOT>;
				clock-names = "ipg", "ahb", "per";
				assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
				assigned-clock-rates = <400000000>;
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				bus-width = <4>;
				status = "disabled";
			};

			sdma1: dma-controller@30bd0000 {
				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
				reg = <0x30bd0000 0x10000>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
					 <&clk IMX8MM_CLK_AHB>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			fec1: ethernet@30be0000 {
				compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
				reg = <0x30be0000 0x10000>;
				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
					 <&clk IMX8MM_CLK_ENET1_ROOT>,
					 <&clk IMX8MM_CLK_ENET_TIMER>,
					 <&clk IMX8MM_CLK_ENET_REF>,
					 <&clk IMX8MM_CLK_ENET_PHY_REF>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
						  <&clk IMX8MM_CLK_ENET_TIMER>,
						  <&clk IMX8MM_CLK_ENET_REF>,
						  <&clk IMX8MM_CLK_ENET_TIMER>;
				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
							 <&clk IMX8MM_SYS_PLL2_100M>,
							 <&clk IMX8MM_SYS_PLL2_125M>;
				assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
				fsl,num-tx-queues = <3>;
				fsl,num-rx-queues = <3>;
				nvmem-cells = <&fec_mac_address>;
				nvmem-cell-names = "mac-address";
				nvmem_macaddr_swap;
				stop-mode = <&gpr 0x10 3>;
				fsl,wakeup_irq = <2>;
				status = "disabled";
			};

		};

		aips4: bus@32c00000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x32c00000 0x32c00000 0x400000>;

			lcdif: lcdif@32e00000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mm-lcdif";
				reg = <0x32e00000 0x10000>;
				clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
					 <&clk IMX8MM_CLK_DISP_APB_ROOT>;
				clock-names = "pix", "disp-axi", "disp-apb";
				assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
						  <&clk IMX8MM_CLK_DISP_AXI>,
						  <&clk IMX8MM_CLK_DISP_APB>;
				assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
							 <&clk IMX8MM_SYS_PLL2_1000M>,
							 <&clk IMX8MM_SYS_PLL1_800M>;
				assigned-clock-rates = <594000000>, <500000000>, <200000000>;
				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
				lcdif-gpr = <&dispmix_gpr>;
				resets = <&lcdif_resets>;
				power-domains = <&dispmix_pd>;
				status = "disabled";

				lcdif_disp0: port@0 {
					reg = <0>;

					lcdif_to_dsim: endpoint {
						remote-endpoint = <&dsim_from_lcdif>;
					};
				};
			};

			mipi_dsi: mipi_dsi@32e10000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mm-mipi-dsim";
				reg = <0x32e10000 0x400>;
				clocks = <&clk IMX8MM_CLK_DSI_CORE>,
					 <&clk IMX8MM_CLK_DSI_PHY_REF>;
				clock-names = "cfg", "pll-ref";
				assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
						  <&clk IMX8MM_CLK_DSI_PHY_REF>;
				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
							 <&clk IMX8MM_VIDEO_PLL1_OUT>;
				assigned-clock-rates = <266000000>, <594000000>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				dsi-gpr = <&dispmix_gpr>;
				resets = <&mipi_dsi_resets>;
				power-domains = <&mipi_pd>;
				status = "disabled";

				port@0 {
					dsim_from_lcdif: endpoint {
						remote-endpoint = <&lcdif_to_dsim>;
					};
				};
			};

			csi1_bridge: csi1_bridge@32e20000 {
				compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi";
				reg = <0x32e20000 0x1000>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
					<&clk IMX8MM_CLK_CSI1_ROOT>,
					<&clk IMX8MM_CLK_DISP_APB_ROOT>;
				clock-names = "disp-axi", "csi_mclk", "disp_dcic";
				power-domains = <&dispmix_pd>;
				status = "disabled";
			};

			mipi_csi_1: mipi_csi@32e30000 {
				compatible = "fsl,imx8mm-mipi-csi";
				reg = <0x32e30000 0x1000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clock-frequency = <333000000>;
				clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
					<&clk IMX8MM_CLK_CSI1_PHY_REF>,
					<&clk IMX8MM_CLK_DISP_AXI_ROOT>,
					<&clk IMX8MM_CLK_DISP_APB_ROOT>;
				clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb";
				bus-width = <4>;
				power-domains = <&mipi_pd>;
				status = "disabled";
			};

			dispmix_gpr: display-gpr@32e28000 {
				compatible = "fsl, imx8mm-iomuxc-gpr", "syscon";
				reg = <0x32e28000 0x100>;
			};

			display-subsystem {
				compatible = "fsl,imx-display-subsystem";
				ports = <&lcdif_disp0>;
			};

			usbotg1: usb@32e40000 {
				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
				reg = <0x32e40000 0x200>;
				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
				clock-names = "usb1_ctrl_root_clk";
				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
						<&clk IMX8MM_CLK_USB_CORE_REF>;
				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
							<&clk IMX8MM_SYS_PLL1_100M>;
				fsl,usbphy = <&usbphynop1>;
				fsl,usbmisc = <&usbmisc1 0>;
				power-domains = <&usb_otg1_pd>;
				status = "disabled";
			};

			usbmisc1: usbmisc@32e40200 {
				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
				#index-cells = <1>;
				reg = <0x32e40200 0x200>;
			};

			usbotg2: usb@32e50000 {
				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
				reg = <0x32e50000 0x200>;
				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
				clock-names = "usb1_ctrl_root_clk";
				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
						<&clk IMX8MM_CLK_USB_CORE_REF>;
				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
						<&clk IMX8MM_SYS_PLL1_100M>;
				fsl,usbphy = <&usbphynop2>;
				fsl,usbmisc = <&usbmisc2 0>;
				power-domains = <&usb_otg2_pd>;
				status = "disabled";
			};

			usbmisc2: usbmisc@32e50200 {
				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
				#index-cells = <1>;
				reg = <0x32e50200 0x200>;
			};
		};

		dma_apbh: dma-controller@33000000 {
			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
			reg = <0x33000000 0x2000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
			#dma-cells = <1>;
			dma-channels = <4>;
			clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
		};

		gpmi: nand-controller@33002000{
			compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
			reg-names = "gpmi-nand", "bch";
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "bch";
			clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
				 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
			clock-names = "gpmi_io", "gpmi_bch_apb";
			dmas = <&dma_apbh 0>;
			dma-names = "rx-tx";
			status = "disabled";
		};

		gic: interrupt-controller@38800000 {
			compatible = "arm,gic-v3";
			reg = <0x38800000 0x10000>, /* GIC Dist */
			      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		ddr-pmu@3d800000 {
			compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
			reg = <0x3d800000 0x400000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	dispmix-reset {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dispmix_sft_rstn: dispmix-sft-rstn@32e28000 {
			compatible = "fsl,imx8mm-dispmix-sft-rstn";
			reg = <0x0 0x32e28000 0x0 0x4>;
			clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>;
			clock-names = "disp_apb_root_clk";
			active_low;
			power-domains = <&dispmix_pd>;
			#reset-cells = <1>;
		};

		dispmix_clk_en: dispmix-clk-en@32e28004 {
			compatible = "fsl,imx8mm-dispmix-clk-en";
			reg = <0x0 0x32e28004 0x0 0x4>;
			clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>;
			clock-names = "disp_apb_root_clk";
			power-domains = <&dispmix_pd>;
			#reset-cells = <1>;
		};

		dispmix_mipi_rst: dispmix-mipi-rst@32e28008 {
			compatible = "fsl,imx8mm-dispmix-mipi-rst";
			reg = <0x0 0x32e28008 0x0 0x4>;
			clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>;
			clock-names = "disp_apb_root_clk";
			active_low;
			power-domains = <&dispmix_pd>;
			#reset-cells = <1>;
		};
	};

	lcdif_resets: lcdif-resets {
		#address-cells = <1>;
		#size-cells = <0>;
		#reset-cells = <0>;

		lcdif-soft-resetn {
			compatible = "lcdif,soft-resetn";
			resets = <&dispmix_sft_rstn IMX8MM_BUS_RSTN_BLK_SYNC>;
		};

		lcdif-clk-enable {
			compatible = "lcdif,clk-enable";
			resets = <&dispmix_clk_en IMX8MM_LCDIF_APB_CLK_EN>,
				 <&dispmix_clk_en IMX8MM_LCDIF_PIXEL_CLK_EN>;
		};
	};

	mipi_dsi_resets: mipi-dsi-resets {
		#address-cells = <1>;
		#size-cells = <0>;
		#reset-cells = <0>;

		dsi-soft-resetn {
			compatible = "dsi,soft-resetn";
			resets = <&dispmix_sft_rstn IMX8MM_MIPI_DSI_I_PRESET>;
		};

		dsi-clk-enable {
			compatible = "dsi,clk-enable";
			resets = <&dispmix_clk_en IMX8MM_MIPI_DSI_CLKREF_EN>,
				 <&dispmix_clk_en IMX8MM_MIPI_DSI_PCLK_EN>;
		};

		dsi-mipi-reset {
			compatible = "dsi,mipi-reset";
			resets = <&dispmix_mipi_rst IMX8MM_MIPI_M_RESET>;
		};
	};
};

Thanks & Regards,

Vasu

Zhiming_Liu · ‎03-11-2021

Hi

Please generate patch file that show me what you changed

imx8m mini custom board uboot issue

imx8m mini custom board uboot issue

i.MX 8M | i.MX 8M Mini | i.MX 8M Nano