imx8 ecspi Master Mode with SS_CTL Control

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imx8 ecspi Master Mode with SS_CTL Control

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757048156
Contributor I

the IMX8MDQLQRM  chepter 10.1.4.4.1.3 (page 3347) sayWhen the SPI SS Wave Form Select (SS_CTL[3:0]) is set,the SS will negate between SPI bursts until the wait states finish

but it didnt work

i set the sample period control register to 5 

devmem2 0x3083001c
/dev/mem opened.
Memory mapped at address 0xffff86795000.
Read at address 0x3083001C (0xffff86795018): 0x0000000500000083

the SS_CTL[3:0] is 1 

0x30830008
/dev/mem opened.
Memory mapped at address 0xffffb4c38000.
Read at address 0x30830008 (0xffffb4c38008): 0x0000010001F091F1

pastedImage_54.png

if all is fine,the ss (ce)line will negate at red point

how can i fix this

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4 Replies

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christoph_fauck
Contributor I

Hi,

I've the same issue on MIMX8MM6 and therefore switched to current SDK 2.8. The fsl_ecspi.c file still configures the SMC flag to one which ignores the SS_CTL flag.

So I configured this manually and working by filling the fifo and sending using XCH flag, but the chip still ignores the SS_CTL flag and inactivates the chip select between the bursts.

It seems to be a chip errata.

- Christoph

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  This is a CSPI feature - the maximum length of a single SPI burst is not defined in the BURST LENGTH

field of the ECSPI_CONREG control register, but  really the maximum length of the single SPI burst is

defined by FIFO. When FIFO is underflowed (empty) the SS is negated.  

   ECSPIx_PERIODREG may be used to setup delays between SPI transfers.

 

Regards,

Yuri.

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christoph_fauck
Contributor I

Hi Yuri,

thanks you very much and yes, I know. I configured the burstlength to 8, cleared SMC bit, cleared SS_CTL bit, filled the txdata-fifo with some words and send using XCH bit. So the fifo contains multiple words and the SPI module has to send within the same chipselect frame. But it sends each byte of a fifo word in an own chipselect frame.

For avoid misunderstanding by me I played with all four possible combinations given by SS_CTL and SMC bit.

- Christoph

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi 刘 

one can try that functionality with SDK_2.6.0_EVK-MIMX8MQ available on

Welcome | MCUXpresso SDK Builder 

Best regards
igor
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